針對3D整合之電子設計自動化技術開發---子計畫三：針對三維規則型邏輯結構之架構探索及穩健合成系統開發(I)

Abstract

隨著製程演進至深次微米，單一晶片可整合更多之電晶體數目及功能模組。同時單一元件的切換速度愈來愈快，進而提高元件的工作時脈頻率。然而，在系統中無可避免地會需要模組間的資料交換，這意味著在傳統二維晶片上將存在著長導線用以連接不同的模組。不同於單一元件藉由製程進步得到速度的提昇，這些長導線因為元件的縮小而導致傳輸速度惡化，反而限制了整體系統效能上的增進。所以當二維平面的擴展因而受到了限制後，轉向垂直方向來拓展空間是一種頗值得期待的作法，故三維的電子系統架構(3D architecture)便因此而被提出。另一方面，異質整合(heterogeneous integration)的困難為系統單晶片(system-on-a-chip, SoC)所面臨的一個大問題，混合製程(mixed process technologies)更限制了系統優化的可能性。而三維架構更是為此提供了一個可行的解決方案。 三維規則型邏輯架構之推廣與應用所面臨的眾多挑戰之一是缺乏量身訂做的設計自動化工具(design automation tools)。本計劃將針對三維規則型邏輯結構(3D regular logic structure)發展相對應之自動化設計演算法；包括效能導向(performance-driven)之邏輯區塊擺放(placement)演算法，以及有高容錯能力的穩健合成(robust synthesis)演算法。並利用這些新開發的工具來進行三維規則型邏輯結構之架構探索(architecture exploration)，以期在硬體資源的使用、系統容錯能力和系統效能之間取得最佳平衡。

As advancing into the deep-submicron era, more transistors and functional modules can be integrated into a single die. The increasing switching speed of a semiconductor device is boosting the operating frequency as a consequence. However, it is unavoidable that modules within a system need to communicate with each other, which implies long interconnects are mandatory for inter-module communication in a traditional two-dimensional chip. In contrast with a single device whose speed is getting faster as the manufacturing process advances, the decreasing speed of these long interconnects seriously limits the improvement of system performance. Hence, space expansion through the vertical direction is considered as a very promising alternative as the expansion in 2D plane is apparently bounded. As a result, 3D architectures are proposed. Meanwhile, the technical difficulty of heterogeneous integration is a very big challenge in SoC while mixed process technologies on a single die prevent many optimization opportunities as well. Therefore, 3D architectures provide another possible solution to the above issues. One of the tough challenges for the broad applications of 3D regular structure is the lack of Electronic Design Automation (EDA) tools. In this project, we intend to develop the advanced algorithms targeting 3D regular logic structures. They include a performance-driven logic block placement algorithm and a robust synthesis algorithm aiming high fault-tolerance capability. Furthermore, by utilizing the newly developed dedicated algorithms, we can explore more advanced architectures for 3D logic structures to achieve the perfect balance among hardware utilization, fault-tolerance capability and system performance.