針對3D整合之電子設計自動化技術開發---子計畫二：三維電路整合之實體設計系統(I)

Abstract

新興的三維電路整合技術可以突破傳統二維晶片的限制，包括縮短繞線長度，提高封裝密度， 在PC 板上占用較小的面積，異質技術整合。理論上，單一顆三維積體電路可以包含數十片的 傳統二維晶片，遠大於現有技術所能達到的容量。這是三維電路之所以吸引人的原因。因此， 嶄新的實體設計技術與方法是迫切需要的。 此計畫將實體設計分成兩大部分，第一年我們發展一套電路切割與擺置的自動化系統，第二 年主要是開發兼具考量導線長度與散熱的繞線系統。 在三維電路中，所有的輸入與輸出訊號都必須經由最底層的晶圓才能與外界溝通；這個特性 使得傳統的電路切割演算法無法再保證得到最佳的結果。因此，在第一年我們會針對此一特性 發展一個電路切割的方法；並且發展一套擺置的方法兼顧矽穿孔 (Through-Silicon Via)附近的擁 擠度與總線長。 三維晶片的繞線問題除了要考量傳統的訊號延遲問題外，也須要考慮到散熱的問題。由於散 熱在三維晶片是相當重要的問題，而矽穿孔被用來連接不同層晶圓間的導線也兼具幫助中間晶 圓散熱的功能。第二年的繞線研究主題將著重在貫穿晶圓節點的擺置以及散熱導向的繞線器的 研究，發展一個減少導線長度儘量避開溫度較高區域以及有效利用貫穿晶圓節點的三維晶片繞 線器。

3D integration is emerging as an attractive way to sustain Moore’s law and even to enable more than Moore. The key benefits of 3D ICs over traditional 2D chips include reduction of the global interconnect length, higher packing density, smaller footprint, and the enablement of mixed-technology integration. The theoretical possibility of integrating tens of die in a 3D IC can usher in a new era of computational platforms with capabilities that are far beyond what is currently possible. Hence, novel physical design techniques and methodologies for 3D integration are desired. This project divides the physical design tasks into two parts. In the first year, we develop an automation tool for partitioning and placement, while, in the second year, we devise a global and detailed router considering wire-length minimization and hot-spot region avoidance. Because all interactions with external signals have to be through the bottom layer, the conventional partitioning and placement algorithms cannot guarantee optimality for 3D integration anymore. Thus, we shall develop a partitioner that can minimize the number of through-silicon-vias (TSV) used. Based on this partitioner, we then devise a placer that considers congestion around TSVs and total wirelength accordingly. In the design of 3D IC routing, traditional signal delay as well as thermal effects are both important issues. TSVs are employed to connect different designs in adjacent silicon layers; besides thermal effects of the designs below the top silicon layer are also delivered through TSVs. In second year, we develop an efficient placement of TSV for temperature reduction and resource optimization. Furthermore, we also develop a thermal-driven 3D global router and detailed router based on a simple and fast thermal model. Traditional wire-length minimization is also taken into account in our router.