用於快閃式記憶元件及電路性能與可靠性模擬的元件模式

標題:	用於快閃式記憶元件及電路性能與可靠性模擬的元件模式 A Compact Spice Model for Performance and Reliability Simulation of Flash EEPROM Cells and Circuits
作者:	莊紹勳 Chung Steve S 交通大學電子工程系
關鍵字:	快閃式記憶體;閘極電流模型;汲極電流模型;SPICE模型;電路模擬器;Flash memory;Gate current model;Drain current model;SPICE model;Circuit simulator
公開日期:	2000
官方說明文件#:	NSC89-2215-E009-046
URI:	http://hdl.handle.net/11536/101626 https://www.grb.gov.tw/search/planDetail?id=542121&docId=99587
Appears in Collections:	Research Plans

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