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dc.contributor.authorChuang, HHen_US
dc.contributor.authorShung, CBen_US
dc.date.accessioned2014-12-08T15:02:20Z-
dc.date.available2014-12-08T15:02:20Z-
dc.date.issued1996-10-01en_US
dc.identifier.issn0916-8532en_US
dc.identifier.urihttp://hdl.handle.net/11536/1017-
dc.description.abstractA new technology mapping algorithm is developed on a general model of FPGA with composite logic block architectures consisting of different sizes of look-up tables (LUTs) and possibly different logic gates. In additions, the logic blocks may have hard-wired connections and limit accessible fanouts. Xilinx XC4000 is one one example containing LUTs of different sizes and AT&T ORCA is another example containing both LUTs and logic gates. We use a multiple-fanout pattern graph library to model the composite logic block and a premapping technique to generate the subject graph dynamically. A new matching algorithm and a new covering algorithm are also developed for the subject graph covering. The experimental results show that our algorithm is an effective technology mapper for FPGAs with composite logic block architectures, especially for large circuits. Over a set of MCNC benchmarks, our algorithm requires on the average 4.25% few CLBs than PPR, 6.79% fewer CLBs than TEMPT, and 2.79% fewer CLBs than ASYL when used as the XC4000 mapper. Over a set of larger benchmarks, our algorithm outperforms PPR by 13.70%. Very encouraging results were obtained when our algorithm is used as an ORCA mapper, while there was no prior published results.en_US
dc.language.isoen_USen_US
dc.subjecttechnology mappingen_US
dc.subjectFPGAen_US
dc.subjectsubject graphen_US
dc.subjectpattern graphen_US
dc.titleTechnology mapping for FPGAs with composite logic block architecturesen_US
dc.typeArticleen_US
dc.identifier.journalIEICE TRANSACTIONS ON INFORMATION AND SYSTEMSen_US
dc.citation.volumeE79Den_US
dc.citation.issue10en_US
dc.citation.spage1396en_US
dc.citation.epage1404en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
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