奈米級混合信號式電路技術---子計畫二：應用於奈米CMOS ICs之Gm-C類比濾波器設計技術(I)

Abstract

在現今進步的製程技術，CMOS 製程已經由深次微米朝向奈米技術的發展，由於 奈米技術的使用，短通道效應影響轉導放大器的線性度效能越來越明顯，而電晶體飽和 區的公式將會受到短通道效應的嚴重影響，因此許多由理想電流公式所衍伸出的傳統轉 導放大器架構在先進的製程中所受到的非理想效應，比起過去製程將會更多。同時在深 次微米的製程技術中，工作電壓也漸漸的下降，電晶體的臨界電壓值越來越小，這樣的 環境下，電路設計上面臨了許多的挑戰。在現今可攜式裝置中，低功率低消耗的特性要 求越來越高下，新製程下的設計與研發都具有相當的前瞻性以及發展性。 由於數位電路的盛行以及電腦輔助工具的成熟，CMOS 元件的電子特性針對了數位 電路的使用達到最佳化的設計。當我們使用的元件達到奈米的階級，數位電路的整體效 能將不會受到影響而被降低，但對於類比電路而言，所需維持的效能諸如：增益、頻寬、 動態範圍以及線性度將會受到很大的影響。因此我們必須針對奈米製程發展適當的類比 電路架構。除此之外，隨著高位元速度的應用需求，類比電路將必須工作於較高的速度 以符合所需，同時其效能必須維持在同樣的水準。 在本計畫中，我們將以奈米CMOS 技術來研究並設計GM-C 濾波器。首先，我們 將以CMOS 技術設計轉導放大器，此放大器將使用電流回授技巧，以做為操作於寬頻 濾波器的基本方塊。由於短通道效應的產生，電晶體的電流與電壓不呈現線性的關係， 設計一個寬頻且線性的運算轉導放大器將會是一個很大的挑戰。經由規格的考量與電路 架構的選定，我們將能設計出所要求的濾波器。最後，我們將依照電路特性做進一步之 調整與建檔，以做為接下來奈米製程之設計考量。 在我們的研究當中，我們的目標為轉導放大器以及轉導電容式濾波器。轉導放大器 為一基本的電路元件方塊，其功能為線性的轉換輸入電壓至輸出電流，此放大器可用於 乘法器、壓控震盪器、轉導電容式濾波器以及連續時間三角積分調變器。在此計畫當中， 我們將所設計的轉導放大器使用於轉導電容式濾波器，並期望此濾波器能適用於無線以 及有線的傳輸系統當中，同時我們將使用奈米製程來設計所需的電路。於第一年將使用 65nm 的製程設計工作於80MHz 速度的轉導放大器與濾波器，同時此電路能達到-70dB 的線性度。接著我們在第二年使用45nm 的製程來設計高速電路，此電路將可工作於 250MHz 的速度並達到-60dB 的線性度。在最後的一年內，我們將使用32nm 的製程來 設計高速與高線性度的電路，此電路將工作於1GHz 的速度並將達到-60dB 的線性度。 因此，本計畫的執行將能實現出寬頻線性濾波電路，並藉由製程的進步以創新的觀 念設計更新穎的電路架構，期許能以不同的方式開創出前瞻性濾波電路，再以此架構為 藍本與其他分項子計畫做進一步之整合，以達到系統整體之最佳化。

With the progress of modern technology, CMOS process has advanced from deep submicron scale to nano scale, which means that the minimum feature size of an MOS transistor has been continuing decreasing. With the scale-down of the transistor sizes, more and more circuits can be integrated in a single chip so that the circuit area and its cost can be reduced. However, the short channel effect has much more impact on nano-scale analog circuit design than in submicron scale. Furthermore, the power supply voltage will be reduced as well and thus increase the difficulty of the circuit design. For the portable devices, low power consumption is essential, which imposes another challenge on the research and development of the nano-scale circuits. Because of the popularity of the digital circuits and also the maturity of their computer-aided design tools, the electrical characteristics of MOS transistors are optimized mainly for digital circuits. Switching to nano-scale technology, digital circuits do not suffer from the degradation of their performances too much. On the other hand, for analog circuits, the circuit performances, such as gain, dynamic range, speed, bandwidth, linearity, etc., are strongly affected by using nano-scale technology. Therefore, new design techniques for nano-scale analog circuits are required to be developed. Moreover, we are living in an analog world, so it is inevitable to use analog signal processing. Modern analog and mixed-signal VLSI applications in areas such as telecommunications, smart sensors, battery-operated consumer electronics, and artificial neural computation require CMOS analog design solutions. Thus, analog signal and information processing in nano-scale technology is really a field in which devotion of efforts is eager. In this research, we will design Gm-C filter by using nano-scale technology. We will design the OTA as the building block by CMOS process. The output current would not easily maintain a linear relationship with the input voltage owing to the short channel effect. Therefore, to design a wideband linear OTA would be a big challenge. Furthermore, we will choose a suitable filter architecture for the specification and design the Gm-C filter by the advanced nano-scale technology. With the advent of nano-technology, in the first year, we will work on the high linearity OTA and Gm-C filter by using 65nm technology to implement the circuits. The linearity performance would achieve -70dB THD at the speed of 80MHz. In the second year, we will develop the high speed OTA and Gm-C filter. We will use 45nm technology to implement the high speed circuits. The linearity performance would achieve -60dB THD at the speed of 250MHz. In the third year, we will continue developing the OTA and Gm-C filter with the even advanced technology. We can use 32nm technology to implement the circuits. The linearity performance would achieve -60dB THD at the speed of 1GHz. Consequently, with innovated design and the progress of process, novel concepts of circuit designs will be investigated to drive the circuits to their utmost. Inevitably, our high speed high linearity analog filter will be integrated with the components in the other sub-projects to achieve an excellent system.