高性能多閘極奈米元件技術

Abstract

此三年期計畫將整合過去「金屬閘極金氧半場效電晶體關鍵技術」以及「新型絕緣 層上覆晶奈米元件」兩個三年期計畫成果，開發具單一金屬矽化物、單一金屬閘極、高 介電常數介電質、調變蕭基位障接面、低溫製程(<600°C)等特徵的多閘極元件及相關製 程、測試、分析技術。 由於採用多閘極元件結構，屬於全空乏型元件，可以避免通道區的濃度變異對元件 特性的影響。全空乏型元件對閘極功函數的需求只需要比能隙中間值高低0.2-0.3eV，故 可以採用全金屬矽化閘極加上離子植入調變達成。源極/汲極採調變蕭基位障接面，故 N-型電晶體以及P-型電晶體可以和閘極使用同一種金屬矽化物，利用同一次金屬矽化製 程完成金屬矽化物成長，再利用同一次離子植入，達成接面製作以及閘極功函數調變的 目的。因為離子植入並未損傷矽晶區域，退火溫度可望控制在600°C 左右，抒解金屬閘 極/高介電常數介電質/矽基板間的熱穩定性問題。金屬閘極可以減少聲子散射，降低高 介電常數介電質對通道載子移動率的影響，多閘極元件的(110)側面通道也有提高電洞移 動率的作用。我們相信這樣的元件技術，是最符合45 奈米製程點之後的奈米元件。 第一年度進行金屬矽化物奈米線的製程研究、建立金屬閘極/高介電常數介電質/矽 基板介面分析技術、多閘極元件製作。第二年度將以第一年度建立之IETS 技術探討製 程條件對介面的鍵結狀態的影響，瞭解側面通道表面形貌與載子移動率的關係，探討奈 米金屬矽化物線的製程限制以及接面性質，並以數值模擬分析元件結構。第三年度將根 據第二年度分析結果，整合最適當的製程條件，製作高性能之多閘極奈米元件，並分析 元件射頻特性以及可靠度。

This 3-year project will integrate the results of the past two 3-year projects of 」 Key technology of Metal Gate MOSFET」 and 「Novel SOI Devices」 to develop a novel multi-gate nano device structure and related process, characterization and analysis technologies. The multi-gate nano device features with single metal silicide, single metal gate, high-dielectric constant gate dielectric, modified-Schottky-Barrier junction, and low temperature process of lower than 600°C. Due to the multi-gate structure, the fully depleted device does not suffer from the dopant fluctuation problem of channel region. The work function of gate electrode could be higher or lower than mid-gap energy by 0.2-0.3eV. This work function modulation can be achieved by fully-silicided (FUSI) gate and dopant implantation. Only one silicidation process is needed to form MSB junction and FUSI gate. The same ion-implantation process can be used to form MSB junction and to adjust work function. Since ions are not implanted into Si region, the annealing temperature can be as low as 600°C. The mobility degradation due to high-k dielectric can be relaxed by metal gate screening of phonon-scattering. The hole mobility can be compensated by the higher mobility of the (110)-oriented sidewall channels. It is believed that the proposed device would be the best candidate beyond 45 nm technology node. In the first year, we will fabricate the nano silicide wire, set up the interface analysis technologies for metal/high-k and high-k/Si interfaces, and fabricate the multi-gate device. IN the 2nd year, the IETS technique and backside analysis technique setup at the first year will be employed to investigate the impact of interface bonding and composition on device performance. The effect of surface roughness on mobility at sidewall channels will be studied. The MSB junction characteristics and contact resistance on nano wires are also examined. The optimum device structure will be simulated by technology computer-aided design tools. The optimal process condition and device structure will be integrated at the third year to demonstrate high performance multi-gate nano device. The reliability evaluation and RF characterization will be performed as well.