利用氟氮摻雜與低溫電漿處理在奈米金氧半電晶體元件製程上的應用

Abstract

隨著半導體技術的演進，未來的元件將趨向更小尺寸、更低阻抗以達到更高速度，因此必須降低閘極的寄生電阻。以金屬矽化物與金屬閘極取代傳統的複晶矽閘極是很有效的方法，然而若使用金屬矽化物閘極，所含金屬容易因高溫製程而滲入閘極絕緣層，而使之劣化；若使用金屬閘極，受限於其製程步驟，閘極氧化層必須以低溫形成。此兩種閘極電極的製程都會造成閘極氧化層的漏電流偏高、可靠度不足。若以高介電係數材料取代二氧化矽。對高介電係數材料二氧化鈦(TiO2)而言，矽基材及二氧化鈦間的界面層(interfacial layer)會導致介電係數下降、界面缺陷增加、可靠度降低。再者，隨著元件的縮小，短通道效應愈來愈顯著，如何形成超淺接面以降低短通道效應的影響也是十分重要的關鍵。 在本論文中，我們提出以三氟化氮(NF3)氣體對鈷矽化物之多晶矽閘極做退火處理，用以改善閘極氧化層的特性，並利用氟與氮的離子佈植來區別其最佳化的條件。另一方面，我們使用四氟化碳（CF4）電漿對矽基材預處理，再成長低溫閘極氧化層與穿隧氧化層。四氟化碳電漿中的氟能修補界面處的不完全鍵結，減少界面缺陷；氟亦能促進低溫氧化層再鍵結而更為緻密，因此所形成之低溫閘極氧化層與穿隧氧化層都具有良好的特性。再者，四氟化碳電漿有蝕刻作用，適當控制後能用來去除高介電係數材料的界面層，從而改善二氧化鈦介電層的特性。 最後，根據上述的低溫超薄氧化層的形成方式，我們提出了一種在奈米金氧半元件形成超淺接面的方法，可以利用既有的離子佈植和快速退火技術來形成超淺接面，毋須使用低能量離子佈植機台。Implanting through amorphous silicon（ITA）是以離子植入非晶矽與超薄氧化物堆疊覆蓋層，並且形成一超淺接面。其中超薄氧化層的作用為蝕刻阻擋層，而且不會降低淺接面的載子濃度。在這種非晶矽-氧化層的雙層結構中，非晶矽層容易剝除，因此有較好的製程控制能力及較高的元件可靠度。

As advances continue to be made in semiconductor technology, smaller and faster devices depend on reducing parasitic resistance. Replacing conventional polysilicon gates with metal polycide and metal gates effectively reduces gate parasitic resistance. However, metal diffusion during the polycide process degrades the gate oxides. High quality low temperature gate oxide with negligible interface states must be formed because of the temperature limits in metal gate processes. These two processes cause the problem of severe leakage and the failure of gate oxides. High-k materials are candidates for future gate insulators. Unfortunately, the interfacial layer between Si/TiO2 high-k materials is a serious problem, lowering the k-value and degrading the high-k film. Additionally, the short channel effect becomes more serious as devices are scaled. The formation of an ultra shallow junction is also important. This thesis investigates a novel process, NF3 annealing of polysilicon gate, to improve the integrity of the gate oxide during the Co polycide process. The optimization of conditions by implanting fluorine/nitrogen is also demonstrated. Based on the merits of fluorinated oxides, additional CF4 plasma pretreatment is proposed to generate high quality low temperature gate oxides and high performance tunnel oxides. Incorporated fluorine can replace dangling bonds, reduce numbers of interface states and enhance re-oxidation. Consequently, high quality, low-temperature gate oxides and high performance tunnel oxides can be produced by CF4 pretreatment. Furthermore, the interfacial layer between Si/high-k films can be removed by the slight etching of CF4 plasma. Therefore, CF4-pretreated high-k films exhibit good electrical characteristics and reliability. Finally, with reference to the formation of ultra thin low-temperature oxides, a new ultra-shallow junction formation method for nano-MOS technology applications is proposed. A method is presented for fabricating ultra-shallow junctions using conventional ion implantation and rapid thermal annealing techniques without the need to use low energy implanting equipment. Implanting through amorphous silicon (ITA) is performed by junction implant through an amorphous-Si/SiO2 stacked layer to form an ultra shallow junction. An ultra thin oxide is grown as an etching stop layer without decreasing carrier concentration. This bilayer amorphous-oxide structure enables the amorphous layer to be easily removed and provides good process control and device reliability.