後次微米時代新興電子設計自動化技術之研究---總計畫(I)

Abstract

半導體元件尺寸隨著製程的持續進步而逐年縮小，可整合於單一晶片上的電晶體數 量也因此增加，讓當今的電子產品得已提供更多、更複雜的功能。然而，在進入深次微 米時代後，製程上的變異及物理效應對於晶片的影響也愈來愈顯著，使得晶片設計面臨 許多新的挑戰，在設計的各個環節上更需重視先進製程可能發生的問題，方能提昇晶片 的品質及可製造性。 本計畫針對設計深次微米時代所需的技術，以分項方式個別研發新興電子設計自動 化軟體，總計畫則以協調各子計畫的相關成果，整合為一由上而下之完整解決方案。所 涵蓋之六項子計畫如下：符合次世代晶片上通訊思維之具備幾何考量的系統架構合成技 術(子計畫一)、整合性低耗電管理之技術開發(子計畫二)、角落錯誤之矽除錯(子計畫 三)、應用計算智慧推理處理後深次微米時代電路設計上的可靠度挑戰(子計畫四)、考慮 可製造化、可靠度與良率的繞線系統(子計畫五)、及後佈局階段貫穿點及導線良率改善 技術之研究(子計畫六)。這些完整而深入的技術開發，預期可以適切地解決這些深次微 米時代所衍生的問題，同時提高國內半導體相關產業之競爭力。

As semiconductor devices shrink with the advancing process technology, more and more transistors can be integrated in a single chip. It makes modern electronic products provide much more functionalities, and increases the complexity to design a chip as well. In addition, the impact of process variation during manufacturing and other physical effects become more and more significant and non-negligible in the era of deep submicron (DSM). New challenges and new design issues arise along with the DSM. Therefore designers must resolve these issues by considering all design stages simultaneously to increase the quality and manufacturability of chips. Because the DSM issues and targets of different design levels are quite diverse, this project considers the overall design flow and divides it into six major topics for advanced research： (1) Geometry-Aware Architecture Synthesis for Next-Generation On-Chip Communication Paradigm, (2) Integrated Low Power Management Technologies, (3) Silicon Debug for Hard-Corner Design Errors, (4) Coping with Reliability Challenges to Circuit Designs beyond Deep Sub-Micron Era by Computational Intelligence Reasoning, (5) Manufacturability, Reliability, and Yield-Aware Routing System, and (6) Yield-Preferred Redundant Via and Wire Insertion with Critical Area Analysis in Post-Layout Stage. The ultimate goal of this project is to integrate these emerging EDA technologies as a complete top-down solution. The techniques developed by these proposed sub-projects will efficiently solve the DSM issues. Furthermore, with the benefit of better design quality and faster design process, the domestic semiconductor related industry will have better competitiveness.