使用60GHz之室內十億級位元傳輸率之無線基頻傳收機---子計畫三：針對通訊數位訊號處理器之電子系統層級驗証與合成環境(I)

Abstract

在傳統的數位系統設計中，通常從一個高階抽象層的描述語言開始設計，如C/C++或MATLAB。經過驗証所設計的演算法與規格相符後，設計者開始手動轉換這些演算法到硬體設計。由於演算法通常使用高精度浮點運算 (floating point, FP)。然基於性能和成本的考量，硬體通常只使用定點運算 (fixed point, fp)。因此，浮點數至定點的轉換是一定需要。其中一個主要的設計挑戰，是以有限位數計算結果，同時維持正確性。 此外，傳統的高階合成流程 (high-level synthesis flow)中所需要的位元數是由設計者指定，而不是設計工具自動決定。在日益複雜的系統中，設計者手動最佳化位元數不再是容易的事。因此，精確的位元數分析應該納入目前的合成流程。在本計畫中，我們將提出一個浮點數到定點數的驗証及合成系統 (Floating Point to Fixed Point Conversion, FP2C)自動將高階層的浮點演算法轉化為低階層定點數的硬體實作。 在計畫的第一年裡，我們將著重於自動量化 (autoqunatization)的過程並且考慮硬體需求。在傳統的設計流程中，通常在演算法階層執行量化過程，完全沒考慮未來硬體需求。有可能導致一個非最佳的硬體設計。相反地，在執行量化的過程中，先將系統架構納入考慮，再驗証量化的結果是否符合設計要求，將能讓系統設計最佳化。一個管線架構的FFT處理器的個案研究，將用來示範新建議流程所帶來的改善。 在計畫的第二年裡，我們將著重於多位元的運算單元 (functional unit)排程(scheduling)與配置(allocation)。我們不但考慮運算單元的種類，還將考慮運算單元的位元數，並且動態地同時執行運算單元排程與配置的動作，讓新提出的驗証及合成流程能將設計的硬體面積縮到最小。 在計畫的第三年裡，我們將著重於連線導向的多位元暫存器配置與綁定 (binding)。除了暫存器的數目會影響到硬體面積，此外，暫存器的位元數與連接的導線亦可能嚴重影響硬體面積。因此，我們將提出新的演算法，藉以減少整體硬體所需之面積。

In traditional digital system designs, it usually starts from pure software descriptions in a high-level language, such as C/C++ or MATLAB. After algorithms are verified to meet the specifications, designers have to manually convert those algorithms into hardware. The algorithms implemented in high-level languages usually use high-precision floating point (FP) operations. Due to performance and cost consideration, the hardware only uses fixed point (fp) operations to implement. As a result, the conversion from floating point to fixed point is mandatory. Hence, one of the main design difficulties is to compute each value using the limited bit-width while maintaining the correctness of results. Meanwhile, in the conventional high-level synthesis flow, the required bit-width of each variable is manually specified but not automatically synthesized by tools. As the complexity of systems and pressure of time-to-market is increasing, the bit-width optimization is no longer manageable by designers. Consequently, the precise bit-width optimization is necessary to take into consideration in the current design flow. In this project, we will propose a Floating Point to Fixed Point Conversion (FP2C) verification and synthesis environment to automatic convert high-level floating point algorithms into low-level fixed point hardware. In the first year, we will focus on the auto-quantization technique with hardware consideration. In traditional design flow, the quantization is performed at the algorithm level without considering the future hardware implementation. It is possible to result in a sub-optimal hardware design. In the contrary, we will perform quantization after mapping to a given system architecture and verify whether the results meet the quantization constraints. A case study of the pipelined FFT processor will be given to demonstrate the effect of our proposed method. In the next year of this project, we will focus on the multiple-bit-width functional units scheduling and binding. As well as the types of functional units, we will also adopt the bit-width into the proposed verification and synthesis environment. Besides, the functional units scheduling and binding are simultaneously performed to explore an area-efficient design. In the last year of this project, we will focus on the interconnection-oriented multiple-bitwidth registers allocation and binding. The hardware area will be certainly affected by the number of registers. The bitwidth of the allocated registers and the interconnection of data paths also play a crucial role. As a result, we will propose an algorithm to minimize the overall hardware area.