新式結構與高介電常數閘極介電層在複晶矽薄膜電晶體之應用(I)

Abstract

利用複晶矽薄膜電晶體製作畫素元件及週邊驅動電路並將之積體化於大面積玻璃 基板已是未來製作平面主動式陣列液晶顯示器(AMLCD’s)的趨勢。本計畫中我們提出數 種改善複晶矽薄膜電晶體特性的技術，包括以兩種高介電常數材料來取代傳統的二氧化 矽當作複晶矽薄膜電晶體的閘極介電層、整合高介電常數閘極介電層與金屬誘發側向結 晶(MILC)法於複晶矽薄膜電晶體的應用、以及新式結構之互補式金氧半反向器之複晶矽 薄膜電晶體。 以新式的高介電常數材料如二氧化鉿(HfO2)及氧化鐠(Pr2O3)當作複晶矽薄膜電晶 體的閘極介電層，預期可誘發較高的閘極電容密度，以產生大量的載子迅速的填補 複晶矽薄膜中的晶粒邊界缺陷。並以二氧化鉿閘極介電層之複晶矽薄膜電晶體來研 究其相關的可靠度劣化機制以及對於複晶矽薄膜電晶體的電與物理特性的影響。並 從結果當中，獲取進一步改善具高介電常數閘極介電層之複晶矽薄膜電晶體可靠度的方 法。另外，本計畫另提出利用低溫(<550℃)鎳金屬誘發側向結晶(MILC)方式製作高品質 之複晶矽薄膜通道，並搭配高介電常數氧化鐠閘極介電層於複晶矽薄膜電晶體之製作， 預期具有較好晶粒結晶性的複晶矽薄膜能有效的減少晶粒邊界缺陷，能更進一步改善複 晶矽薄膜電晶體的電性，如較低的關閉漏電流與較好的導通特性。 另外，本計畫提出一種新結構之複晶矽薄膜電晶體，具有三維堆疊結構之互補式金 氧半複晶矽薄膜電晶體(3-D stacked CMOS poly-Si TFTs)，利用特殊堆疊結構的方式完成 下層為p 型複晶矽薄膜電晶體及上層為n 型之互補式複晶矽薄膜電晶體，藉由在相同的 矽佔地面積裡整合p 型與n 型之複晶矽薄膜電晶體以完成一個簡單的反向器製作，預期 完成複晶矽薄膜電晶體之反向器電路可省下50 %的矽佔地面積以及較少的內部連接 (interconnection)，因此可提升複晶矽薄膜電晶體製成之電路的整體效能。

Utilizing polycrystalline silicon thin film transistors (poly-Si TFT’s) as on-glass pixel switch element and peripheral driver circuits is the future trend for fabricating active-matrix liquid-crystal displays (AMLCD’s). In this project, we propose several technologies to improve the electrical performance of poly-Si TFT’s, including replacing conventional SiO2 with high-k material to serve as the gate dielectric of poly-Si TFT’s, applying the integration of high-k gate dielectric and MILC technique into the poly-Si TFT’s, and proposing a novel CMOS inverter structure of poly-Si TFT’s. Novel high-k materials, such as Hf O2 and Pr2O3, served as the gate dielectric of poly-Si TFT’s are expected to induce higher gate capacitance density, and then produce a large amount of carriers to rapidly fill up the grain-boundary defects of the poly-Si film. Furthermore, we also study the corresponding reliability-degradation mechanisms and investigate the effects of the electrical and physical characteristics on the poly-Si TFT’s with HfO2 gate dielectric. From the results, we will obtain the methods of improving the stress reliability of the poly-Si TFT’s with HfO2 gate dielectric. Besides, this subject also proposes fabricating high-quality poly-Si channel film by a low-temperature (<550 oC) metal-induced lateral crystallization (MILC) technique, and fabricates poly-Si TFT’s with the integration high-k Pr2O3 gate dielectric and MILC technique. We expect that the electrical performance of poly-Si TFT’s can be further improved, including lower off-state leakage current and better on-state property, by enhancing the grain crystallinity and decreasing the grain-boundary defects. Moreover, this subject propose a novel structure of poly-Si TFT’s, 3-D stacked CMOS poly-Si TFT’s. CMOS poly-Si TFT’s can be formed by the special stacked structure of bottom p-type poly-Si TFT’s and top n-type poly-Si TFT’s. A CMOS inverter poly-Si TFT’s can save around 50 % Si occupying area and reduce the interconnection by the formation of p-type and n-type poly-Si TFT’s on the same Si occupying area, improving the circuit performance fabricated by the poly-Si TFT’s.