使用60GHz之室內十億級位元傳輸率之無線基頻傳收機---總計畫(I)

Abstract

本計畫目標在於開發前瞻之室內億級位元傳輸率基頻傳收機之SOC 設計技術及相 關之關鍵性智產平台與設計法則。計畫擬以在制定中適用於室內億級位元傳輸率之無線 基頻傳收機作為技術開發之載具，並將設計延伸至無線高解析多媒體影音介面(Wireless High Definition Multimedia Interface, WirelessHDMI)應用，以設計出相關標準之室內億級 位元傳輸率之無線基頻傳收機之關鍵IP 及系統晶片。計畫目標是發展下列關鍵技術包 括： 1. 室內億級位元傳輸率之無線基頻傳收機及延伸至 WirelessHDMI 基頻傳收機之 系統設計及效能評估。 2. 室內億級位元傳輸率之無線基頻傳收機之高性能、低功率之關鍵軟／硬矽智財 設計，如前端數位重取樣IP，符號同步IP，通道預估IP，載波同步IP，FFT／ IFFT IP，LDPC 編解碼IP，空間—時間解碼IP 等… 3. 多核心及加速數器和平台設計及其在基頻數位信號處理之運算。 4. 前瞻電子層級之合成設計與驗證及系統評估。 5. SOC 整合設計與驗證流程發展。 這些技術分在五個子計畫與總計畫執行，於三年中研發完成。第一年完成各功能方 塊之基頻訊號處理演算法之C (System C)與Matlab 設計及規格訂定，並建立設計與系統 平台與驗證環境，同時開始進行最上層之各功能方塊IP 之C (System C)與Matlab 系統 整合設計。第二年除了完成第一版各關鍵IP 之FPGA 及ASIC 設計及驗證，並利用多 核心平台環境完成評估與系統驗證，並且我們會以第一年基頻傳收機之成果繼續作更進 階之系統規格發展與增進，藉以持續改進設計平台之效能。第三年除了改進前一年之IP 設計外將配合多核心平台和本計畫研發的IPs，作系統雛型驗證與展示。最後也將以所 設計之適用於無線高解析多媒體影音介面之室內億級位元傳輸率之無線基頻傳收機之 各種規格嘗試作多模式之雛型與展示。

The goal of this project is to develop core technologies and design platform for Wireless Personal Area Network (WPAN) baseband transceiver. We will use the under developing standard IEEE 802.15.3c for Multi-Gbps wireless personal area network (WPAN) as our design platform. Furthermore, the system design and IP technologies will try to extend to Wireless High Definition Multimedia Interface (WirelessHDMI) application. The objects are to develop the following core technologies: 1. System design and performance evaluation of broadband transceiver receiver for indoor 60GHz Multi-Gbps wireless baseband transceiver with extension to WirelessHDMI application. 2. Low-power and high-performance ASIC soft/hard IP design for key function blocks indoor 60GHz Multi-Gbps wireless baseband transceiver including front-end digital resmapling IP, symbol synchronizer IP, channel estimator IP, carrier synchronizer IP, FFT/IFFT IP, LDPC codec IP, space-time decoder IP, and etc.. 3. Low-power and high-performance Multi-core platform and accelerator IP designs for those aforementioned related baseband signal processing operations. 4. System evaluation and verification of baseband system by using Multi-core platform. 5. Electronic System Level (ESL) synthesis and verification methodology for communication IPs. 6. System integration, realizations and demonstrations. All these core techniques will be developed by group project and five subprojects in three years. In the first year, the algorithm of indoor 60GHz Multi-Gbps wireless baseband transceiver will be coded in C (System C) and Matlab. The specifications evaluation of each function will also be carried out. The system design flow and integrated methodology will be setup to do system simulation. In the second year, the key modules and IPs will use FPGAs and ASIC to verify their functionality and performance. Multi-core development environment will be used to do the performance evaluation and verification. Also, more advanced specifications will be investigated to improve the performance. In the final year, we will improve the performance of the key IPs and will use Multi-core platform with the developed IPs to do system prototyping and demonstration. Moreover, Multi-mode possibility will be evaluated by combining different spec. of 802.15.3c or other standards.