新穎多孔性氮碳化矽材料及氣隙內連接可行性之研究

Abstract

超大型積體電路元件為降低尺寸縮小所帶來之RC 遲滯效應，在90 奈米後段製程中已引進低 介電材料(k ~ 3.0)。而新世代超低介電材料(k < 2.5)之研發仍以多孔性的低介電材料為主，然而因可 靠度及機械強度不足之故，使其應用上仍有待解決。而較革命性的氣隙內連接，在今年五月IBM 宣佈後，再度點燃產學界研發上的競爭。而目前IBM 氣隙內連接無法被接受之主因乃在於額外光 罩費用和機械強度。為解決這些問題，本計畫提出一種新穎的氣隙內連接結構，其中包括兩大關鍵 性材料：(1)自我對準(self-aligned)的金屬覆蓋層，如CoW(B,P)，以降低電遷移情況並保護銅導 線，及(2)待開發之新穎多孔性氮碳化矽材料(PESL)。 本計畫研究目標可分為三項：(1)研究以旋轉塗佈法和電漿輔助化學氣相沉積法於低溫(< 450 °C)沉積PESL 薄膜，(2)瞭解及建立在低溫下形成nano-或meso-PESL 結構的方法與理論，及(3)驗 證新穎氣隙連接技術之可行性。 本計畫預計分三年期，第一年將以 PECVD 沉積PESL 薄膜為研究主題，研究(1)兩相式 SiNC/porogen 奈米複合材料；(2)接有乙烯基起洞劑之聚矽氮烷(polysilazane)主鏈，和(3)團聯共聚物 (diblock copolymer)型式沉積PESL 薄膜之材料性質。計畫第二年將延伸前一年之研究成果，嘗試以 類似的設計概念，但更容易依據實際需求而量身定作(tailor-making)適用於spin-on 方式沉積的 PESL 薄膜。而第三年將於國家奈米元件實驗室製作單層Cu/low-k 試片及驗證新型氣隙內連接技術 之可行性。另預期PESL 及氣隙成果可移轉至國內半導體公司，增進國內於後段製程之研發技術。

Development of low-k materials has been the primary effort in the backend interconnects to minimize the RC delay in the ULSI devices. Evolutional approach of ultra-low k materials (k <2.5) focuses on porous materials through the incorporation of sacrificial, low- or hightemperature porogens, which still have challenging issues in barrier reliability and mechanical integrity. In contrast, air-gap interconnect is a revolutionary approach capable to deliver keffective close to 1. IBM’s announcement in May, 2007 on air-gap microprocessors has rekindled the pursuit of air-gap interconnects in the microelectronic industry as well as in the academia. Noticeably, additional masks and mechanical reliability are prohibitive to its acceptance for mass production. To eliminate the need of additional masks, we propose a novel air-gap interconnect architecture which involves two critical materials: (1) a well-known metal cap layer and (2) a novel porous etch-stop SiNC layer (PESL). Metal cap layer such as CoW(B,P), which is self-aligned through selective electroless deposition onto Cu lines, can enhance electromigraion resistance and provide protection to Cu lines during any post processing step. PESL, an enabling material technology, can provide permeable channels for plasma etching in the removal of the sacrificial interlayer dielectric (ILD) in forming the air-gap. The objectives of this research proposal are three-folds: (1) to develop a spin-on and a PECVD low-temperature PESL with required selectivity (>10:1) and permeability for removing the sacrificial ILD between the metal lines to form air-gap interconnect, (2) to establish the fundamental understanding and theory of nano- and meso-porous structures in PESL thin films at low temperature < 450 oC, and (3) to demonstrate the feasibility of air-gap interconnect. In the first year we plan to focus on the studies and development of PESL by PECVD deposition based on approaches: (1) two-phase SiNC/porogen nanocomposites, (2) grafting a porogen onto a polysilazane precursor with vinyl groups, and (3) forming a diblock copolymer for ordered pore structure. In the second year, we propose to extend our PECVD PESL research to spin-on PESL materials by taking advantage of its ease in tailor-making of porous structures based on similar PECVD approaches. During the 3rd year, air-gap interconnect will be demonstrated through the fabrication of 1-level Cu test wafers in National Nano-Device Lab. Moreover, the methods for forming a permeable PESL and the kinetics of ILD removal by plasma etching through PESL will be investigated. This enabling novel PESL materials and air-gap interconnect technology are expected to contribute significantly to the backend technology leadership for major semiconductor companies in Taiwan.