具系統面板整合性之前瞻顯示電晶體元件製作與研究

Abstract

本計畫將利用三年的時間來完成『高效能-具記憶體特性之多重奈米線薄膜電晶體』之製作與物理 機制研究。近年來，主動式顯示面板技術蓬勃發展，為了提高面板的應用價值並降低製作成本，因此 產業界期待發展出同時具有記憶體元件與驅動電路的系統整合型面板(system on panel; SOP)。由於複 晶矽薄膜電晶體具有高的驅動電流，因此可取代外接式驅動電路整合於顯示面板中，以做為面板週邊 的驅動元件。在本研究計畫中，將發展一種可應用於系統面板整合性的前瞻顯示元件技術，製作出能 集畫素開關、驅動與記憶體特性於一身的高效能奈米線顯示電晶體，如此將可大大簡化系統面板技術 中元件(即:驅動開關元件與記憶體元件)製程整合的複雜性，可使顯示面板同時具有驅動、讀取及儲存 等功能，有效達到系統整合型面板之目的。在研究中，我們也將應用高介電常數薄膜於電晶體元件中， 藉此提高顯示元件的記憶體功效與電晶體驅動特性；除此之外，我們將發展一種創新的薄膜缺陷鈍化 技術，即：利用超臨界流體(supercritical fluid)技術，在低溫下對多晶矽薄膜電晶體元件內的缺陷進行 鈍化(passivation)處理，可有效取代傳統高溫退火(annealing)及電漿(plasma)的製程，進一步提升顯示元 件特性以及縮短製程時間與製造成本。最後，在計劃中也將對此高效能-具記憶體特性之顯示電晶體進 行操作上的可靠性研究與物理機制探討，以瞭解實際應用於系統面板中可能遭遇到的問題。

This project will be implemented to investigate a high performance nano-wire polycrystalline thin film transistors (poly-Si TFTs) acting as both switch and nonvolatile memory devices during the coming three years. Recently, poly-Si TFTs have attracted much considerable attention for active-matrix liquid-crystal-displays (AMLCDs), since they have high field effect mobility and driving current and can be integrated with peripheral driving circuits. However, the improvement of electrical characteristics and the reduction of undesirable effects are still important issues. The presence of poly-Si grain boundary defects in the channel region of TFT device drastically affects the electrical characteristics and leads to the increased leakage current. Moreover, in order to make display more compact, reliable and further reduction in the cost, system-on-panel (SOP) display integrated with functional devices on the LCD panel, such as driving device, scanner device, controller, and memory, was developed. In this project, we will develop a poly-Si TFT device with multiple nanowire channels and π gate structure to enhance the electrical performance. The proposed poly-Si TFT device can exhibit both high current driving and memory characteristics. This proposed technology is promising to realize the process integration of devices (i.e. switch, driver and memory devices) for SOP device application. Also, a novel defect passivation technology will be developed for the first time to passivate Si grain boundaries and traps in dielectric films via a supercritical fluid treatment. The electrical reliability and physical mechanism for the proposed poly-Si TFT will be studies and deduced in detail. The research is really important for the development of high performance poly-Si TFT technology and the knowledge of carrier transport mechanism in the nano-science physical fields.