混合基片奈米CMOS元件技術中各種應力效應對傳輸特性及可靠性影響的研究

Abstract

為了克服CMOS 元件的微縮極限，90 奈米以下的CMOS 技術上，運用各種應力來增 強通道載子移動率，可以大幅提昇驅動電流大小。這種應力結構，其有效的方法分為 二類，其一是單向應力(uniaxial strain)，屬於一維的形變，以利用製程為之；另一則是 biaxial strain，屬二維的形變，最普遍的方法是將矽通道層長在矽鍺層(SiGe)上面。我 們最近的研究發現，載子移動率提昇越多，元件可靠性將越差，uniaxial strain 或biaxial strain 對電流的提昇，則有不同的效果。本計劃的目的有二：其一是探討各種不同strain 對元件電流提昇的影響，該類元件的彈道傳輸(ballistic transport)特性，另一則是傳輸特 性與可靠性間的關係，以獲致高元件性能及高可靠性的最佳化設計。 本計劃為期三年。第一年目標是研製各種strain(即uniaixal strain、biaxial 及二者組合的 multiple-stressor)的nMOS 元件，進而探討其傳輸特性的量測方法研究。首先，我們須 設計製作超薄閘氧化層(100)-surface nMOS 元件一批，採用不同的strain 方式。其次， 量化元件傳輸特性的主要參數(transport parameter)（入射速度及反射係數），以建立傳 輸特性參數，並且探討該參數與可靠性受應力影響的程度。 第二年計劃，我們將採用不同的strain 結構於pMOS 元件的製作。運用第一年的研究 方式，首先，我們需設計製作各種strain 結構(110)-surface pMOSFET 元件，延續第一 年的transport 理論，實驗計算transport 參數，可靠性量測，尤其探討pMOS 可靠性的 關鍵，即負偏壓不穩特性(NBTI)可靠性。最後則研究應力對於傳輸特性參數及元件可 靠性的影響。探討何種應力結構有較佳的傳輸參數及優異的可靠性。 第三年計劃，運用前二年製作的元件，探討multiple-stressor 元件的傳輸參數及可靠性 建立transport 參數及可靠性的技術藍圖(technology roadmap)，nMOS 與pMOS 元件的 性能與可靠性設計準則及roadmap。這二項成果可以提供未來ITRS roadmap 討論時參 考。將有助於建立下一世代奈米CMOS 元件採用混合式基片(hybrid substrate) CMOS 技術時，strain 結構CMOS 元件的最佳設計準則。

In order to relax the CMOS device physical limit, strain device technology has become a popular technology with gate length below 90nm for achieving high mobility as well as high driving current. Two most popular methods have been adopted to achieve the strain. One is the uniaxial strain using a simple process techniques, the other one is the biaxial strain, mostly with the Ge incorporation. Our recent study showed that with increasing mobility enhancement, it will adversely degrade the device reliability depending on the extent of the uniaxial or biaxial strain. Therefore, the understanding of these problems is critical to use strained-silicon into realistic application for next generation CMOS devices. The purpose of this project are two folds, one is to investigate the various strain effects on the device driving current based on the characterization of ballistic transport parameters. The other one is to study the correlation between transport parameters and the device reliability for achieving best device performance and reliability. This project includes 3 phases. In the first year, the goal is to fabricate various strained nMOSFET』s with (100)-surface and uniaxial strain, biaxial strain, or a combination of both. Then, a systematic method will be applied to experimentally determine the key transport parameters. These two important parameters include the injection velocity and the backscattering coefficient. Finally, the correlation between the transport parameters and the device reliability will be tackled. In the second year, first we need to fabricate (110)-surface pMOSFET』s with uniaxial strain, biaxial strain, or a combination of both. Based on the characterization of transport parameters in the previous year, we may extract similar transport parameters. Device performance as well as HC(Hot Carrier) reliability, NBTI will then be characterized. Finally, the strain effects on the device performance and reliability will be studied. In the third year, based on the previous two years results, similar approach will be applied to the study of multiple-stressor nMOSFET and pMOSFET. The roadmaps on the transport characteristics as well as the device reliability will be provided. These results will be expected to be useful for future ITRS in establishing a roadmap on the strained CMOS technology using the hybrid substrate structure.