奈米點記憶體元件之製作與物理機制研究(I)

Abstract

傳統非揮發性記憶體的基本構成單元主要是由多晶矽(poly-Si)浮閘(floating gate)元 件所構成，為了使得非揮發性記憶體元件有更高操作速度，包覆多晶矽的氧化層需要向 下微縮。然而，這使得多晶矽層內所儲存的電子更容易遺失，導致記憶特性的消失。為 了同時達到高速操作以及長久記憶特性的要求，具有分離式與高密度儲存中心的奈米點 記憶體被提出為解決的方法。奈米點記憶體除了能同時達到非揮發性與高速及低能損操 作的要求之外，同時奈米點記憶體的製程與現有之半導體製程完全相容，而被視為下世 代非揮發性記憶體。 透過金屬奈米點本身具的高度儲存狀態(density of state)以及強耦合能力，可使得奈 米點記憶體能在小電壓操作下即可獲得能夠邏輯電路辦別之記憶準位，而達到高速操作 的特性。此外若取代傳統包覆奈米點的氧化矽材料為高介電材料，能夠產生更強的耦合 能力以達到更高的記憶體元件操作效率。 本計畫主要的目標是非揮發性奈米點記憶體之製作與物理機制研究。第一年將針 對金屬、金屬矽化物與磁性材料物奈米點結合高介電常數絕緣層之製作研究，此外，並 建立DLTS 以及記憶體元件之模擬與量測分析技術。計畫的第一年將利用各種不同的金 屬、金屬矽化物與磁性材料物質結合高介電常數之絕緣物質以製作出金屬性奈米點(W、 Mo、Co 與Ni 等)於高介電常數絕緣層中可有效的增加元件的操作效率。金屬性奈米點 本身因具有高功函數以及強耦合能力，結合高介電常數物質絕緣層所具有之高介電常數 特性進而改善電荷儲存的效率與分析奈米點儲存之物理特性。我們將利用半導體相關的 低溫製程以形成奈米點，以期能應用於薄膜電晶體顯示器產品。後處理製程如氫電漿、 氨電漿與超臨界處理等將研究以改善奈米點本身的穩定度與可靠度。除此之外，我們將 利用DLTS 對載子的儲存機制進行深入的探討與研究，以期瞭解奈米點記憶體的儲存物 理機制，進而改進奈米點記憶體的特性。第二年將針對元件結構改進之製作研究，並將 驗證奈米點記憶體的技術於場效應電晶體以及薄膜電晶體。我們將利用第一年的研究成 果，對記憶體元件結構改進，如多層奈米點等之研究以提升奈米點記憶體元件的儲存能 力並瞭解奈米點儲存之物理機制。最後，將奈米點與場效應電晶體以及薄膜電晶體整 合，並針對各種寫入機制與記憶體特性作探討。本計畫著重於兩部分，一為奈米點記憶 體結合高介電常數物質之元件的製作與後處理製程的影響，另一為奈米點記憶體之物理 特性探討。利用量測電流電壓特性(IV)與電容電壓特性(CV)並搭配X-Ray 光電子能譜圖 (XPS)、二次離子質量頻譜(SIMS)與穿透式電子顯微鏡(TEM)等對所形成之奈米點做物性 的探討。最後歸納奈米點記憶體元件的電特性與材料之間的關係，建立完整的奈米點記 憶體元件資料庫與其物理機制。

Recently, nanocrystals (NCs) memory has received much attention due to its discrete charge storage centers and physics originate from nano scale. It is well know that the unit cell of non-volatile memories (NVMs) is constructed with continuous floating gate (FG) embedded in silicon oxide. In order to gain high operation speed and low power consumption, the oxide layer has to be scaled down. On the other hand, the thick oxide layer is required for non-volatility of NVMs. The nanocrystal memory was proposed as the solution for these conflict requirements due to its properties of discrete charge storage centers and high density of storage states. In addition, NCs memory have been shown to be compatible with semiconductor technology and regarded as next generation NVMs. The recent researches indicate that the metal NCs have advantages of high density of states and stronger coupling with conduction channel, which enable the device operation in low voltage and high speed. Moreover, if the surrounded oxide layer is replaced with high-k insulator can further improve NCs memory performance due to lower voltage drop on high-k material. This project focuses on the fabrication of nanocrystals memory device and investigation on their relevant physical characteristics for application on the novel nonvolatile memory devices. In the first year, we will fabricate NCs composed of several metal materials like W, Pt, as well as metal silicide materials like Ni2Si, NiSi, NiSi2, Co2Si, CoSi, CoSi2 or magnetic metals like Co, Ni, etc. Various high-k materials will be combined with NCs to further enhance the device performance. Moreover, low temperature NCs formation process will be investigation for application on thin film transistor. Post treatment process including H2 plasma, NH3 plasma and supercritical fluid will be investigation to improve reliability of NCs memory device.. In the secondary year, the multi-layer structure of charge storage of NCs device will be studied to further improve the device reliability and operation performance. In addition, we will integrate MOSFET or TFT with the NCs to study various properties of NCs memory and its possibility for application on NVMs. The project is mainly divided into two parts, one is fabrication and formation of NCs device and the other is investigation of physics of NCs device。The IV and CV measurement is employed for investigation of electrical properties. XPS, SIMS and TEM are utilized for material analyses. Finally, we will summary the results of electrical and material analyses into complete database for fabrication and physics of NCs memory.