奈米CMOS之高性能類比數位混合信號關鍵電路設計技術---子計畫一：奈米CMOS射頻與混合訊號模型研發應用於超低功耗與低雜訊設計

Abstract

奈米 CMOS 技術之精進已面臨諸多極限問題，如元件線寬之持續微縮，操作電壓 之降低，動態範圍，雜訊與功耗等。其中低功耗與低雜訊，乃是元件模型與電路設計 領域中最具挑戰性的兩個課題。本計劃擬提出創新的元件與電路操作方法，利用異於 傳統之偏壓結構，以解決CMOS 元件臨界電壓與操作電壓之極限問題，並實現低功耗 與低雜訊之設計。目標為微瓦級之超低功耗，以應用於無線可穿戴式之生醫檢測系統。 此創新之偏壓架構乃以四端元件配合四埠測試結構為基礎，並提出｢動態基極偏壓｣方 法為一最佳方案，以兼顧操作功耗與靜止功耗，並有效應用於奈米CMOS 元件與電路 設計。再者，四端元件可提供較大之操作自由度，例如可同時施加直流與射頻訊號於 各個獨立端點。基於此新穎特性，應用於射頻與混合訊號技術平台，可創造出新的電 路架構，以達超低功耗與低雜訊之目標。 奈米CMOS 技術應用於射頻與混合訊號電路，雜訊乃是另一重要課題，需考量極 低頻至極高頻之特性。極小元件之雜訊量測，乃是高難度的工作，因其雜訊往往夾雜 來自矽基板、探針墊、與傳輸線之耦合效應。因此，如何有效且準確萃取元件之本質 雜訊乃是最基本之核心技術。本實驗室於上一期三年計畫已完成一套創新的｢lossy substrate model｣，可準確萃取奈米元件之本質雜訊。本計劃以此為基礎，將進一步研 究雜訊阻隔法，利用奈米射頻CMOS 技術與先進後段製程研製各種結構，測試其雜訊 阻隔能力與效果，並以驗證過之lossy substrate model 為基礎，開發一可模擬雜訊阻隔 效應之等效電路模型，以正確預測各種奈米元件搭配不同雜訊阻隔結構之效果，同時 可模擬四端元件中動態基極偏壓對於雜訊之影響。 前述研究主題隨之產生新的挑戰與研究子題，如量測、去寄生效應、參數萃取、 與模型開發等。傳統標準之射頻CMOS 模型僅限於三端元件模擬，不適用於四端元件 加上動態基極偏壓。針對射頻與混合訊號電路設計所需模型，其新的研究課題可歸納 為 (1) 次截止區之I-V 模型 : 動態基極偏壓對VT、swing、IOFF 之效應。 (2) 線性與飽和區之I-V 模型 : 動態基極偏壓對於mobility、body charge factor、short channel effects、body RC network 與 self-heating effect 之影響。 (3) 四端元件之C-V 模型 : 動態基極偏壓對於gate capacitance、junction capacitance 與 drain-to-source coupling capacitance 之效應。 (4) 四端元件之雜訊模型 : channel 與gate 電流之熱雜訊於寬頻區間且動態基極偏壓 操作下之特性。Flicker 雜訊於截止區加上動態基極偏壓操作之效應。 本三年計劃擬實現之成果為 (1) 第一年(2008~2009) (a) 建立一完整的四端元件與四埠測試結構與分析方法，研究動態基極偏壓之效應 與最佳化設計。 (b) 建立雜訊阻隔結構與低雜訊量測系統、方法，可適用於極寬頻與不同操作電壓 之量測分析。 (2) 第二年(2009~2010) (a) 開發一套射頻CMOS 元件模型，可準確模擬四端元件於動態基極偏壓下之特 性。此模型可適用於標準電路模擬軟體，以輔助超低功耗之射頻電路設計。 (b) 完成一套寬頻且可微縮之lossy substrate model，以正確模擬奈米元件雜訊特性 與雜訊阻隔效應。此模型可適用於射頻電路模擬軟體，輔助低雜訊電路設計。 (3) 第三年(2010~2011) (a) 設計完成超低功耗射頻電路，包括LNA，mixer 與VCO，應用驗證之動態基極 偏壓法。其低功耗規格為LNA+mixer < 0.5mW 以應用於無線近身網路(wireless body area network)。 (b) 設計完成低雜訊射頻電路，包括LNA，mixer 與VCO，應用雜訊阻隔法與動態 基極偏壓。其低雜訊規格為LNA≤ 2dB，mixer ≤ 8dB。至於VCO，其相位雜訊 規格為−110 dBc / Hz於1MHz offset 操作下。

The advancement of CMOS technology into nanoscale has faced multiple limitations, such as geometry scaling, voltage scaling, dynamic range, noise, and power. Low power and low noise have been identified as the most challenging subjects in nanoscale device modeling and circuit design. In this project, novel operation methods adopting new bias schemes will be explored and developed to solve the limitation in CMOS device VT and VDD scaling. The ultimate goal is to realize ultra-low power toward micro-watt scale aimed for wireless and wearable electronics in e-health applications. Four terminal devices and four-port test structure are the basic building block to implement new bias schemes. A dynamic body bias scheme is proposed as one of the best approaches adapted to nanoscale CMOS device and circuit design in trade-off between the active and standby power. New circuit topologies for ultra-low power and low noise can be created on the RF/MS CMOS platform, with added features and freedom of DC/RF signal supply enabled by the four terminal unit devices. Noises over a broadband of frequencies emerge as a critical concern for RF and MS circuit design using advanced CMOS technology. Noises measured from miniaturized devices are generally overwhelmed with excess noises coupled through the substrate, pads, and transmission lines (TML). An effective and reliable method for intrinsic noise extraction is actually a fundamental work worthy of extensive effort. In this project, noise shielding methods will be investigated through test structure design and fabrication using sub-100nm RF CMOS process with advanced BEOL technology. A scalable equivalent circuit model will be developed for accurate prediction of noise shielding effects in sub-100 nm RF MOSFETs with various layouts and topologies, as well as operation over a broadband of frequencies and biases. This scalable equivalent circuit model is targeted as an extension of our original work – a lossy substrate model with proven success in intrinsic noise extraction and simulation. Furthermore, the influence of dynamic body bias on noises (both RF noises in tens of GHz and flicker noise in sub-100KHz) is identified an interesting subject and may provide a promising solution for both low power and low noise design. The mentioned subjects will bring new challenges in measurement, de-embedding methods, parameter extraction, and modeling associated with four port structures and noise shielding schemes. The standard RF CMOS models generally serve for three terminal MOSFETs with body tied to source ground, but may not fit four terminal devices with dynamic body biases. The potential challenges in RF/MS modeling are identified as (1) Subthreshold region I-V model : dynamic body bias effect on VT, swing, and Ioff (2) linear and saturation region I-V model : dynamic body bias effect on mobility, body charge factor, short-channel effects, body RC network effects, and self-heating effects (3) C-V model of four terminal devices : gate capacitances, junction capacitances, and drain-to-source coupling capacitances under dynamic body biases (4) noise model : thermal noises in channel and gate currents over a broadband of frequencies and body biases, flicker noise of drain current in subthreshold region under dynamic body biases. The major milestones to be realized in this 3-year project are summarized as (1) First year (2008~2009) (a) To build a complete infrastructure and characterization methodology for four terminal devices on four port test structures with dynamic body biases. (b) To develop noise shielding structures and ultra-low noise measurement method for RF noises in sub-100nm devices over a broadband of frequencies (1~18 GHz and 2~40 GHz) and biases (drain, gate, and body biases). (2) Second year (2009~2010) (a) To develop an enhanced RF CMOS model with proven accuracy for four terminal devices under dynamic body biases. The enhanced model can be easily implemented in standard circuit simulators to facilitate low power RF and MS circuit simulation and design. (b) To complete a broadband and scalable lossy substrate model for accurate noise simulation and low noise design. This lossy substrate model can predict broadband noise characteristics for nanoscale devices with various geometries, pad structures, TML topologies, and noise shielding schemes. Furthermore, the lossy substrate model by the form of an equivalent circuit can be easily ported in standard RF/MS circuit simulators to facilitate low noise circuit design. (3) Third year (2010 ~ 2011) (a) To build ultra-low power RF front-end circuits, such as LNA, mixer, and VCO adopting the proven dynamic body bias schemes. The enhanced RF CMOS model with new features valid for four terminal devices can facilitate RF circuit simulation accuracy for ultra-low power design. The low power target is set below 0.5mW under ultra-low VDD for LAN+mixer in wireless body area network (WBAN) for e-health application (b) To develop low noise RF front-end circuits, such as LNA, mixer, and VCO. More stringent noise specification is required LNA than mixer, but more tough challenges in noise measurement and modeling for mixer – a large signal circuit. The low noise target is set below 2dB for LNA and 8dB for mixer. As for VCO, phase noise is dominated by flicker noise in lower frequency and targeted below -110 dBc/Hz is set up under 1MHz offset from center frequency (1.4GHz).