可攜式EEG/EKG/fNIRS腦神經影像系統研發暨其整合型生醫感測處理晶片系統設計---子計畫四：低複雜度生醫運算引擎設計與嵌入式平台建置(I)

Abstract

本計畫為整合型計畫中的子計畫四-低複雜度生醫運算引擎設計與嵌入式平台建置負責進行整合後端EEG/EKG/fNIRS生醫運算晶片設計與製作和3D醫學影像顯示嵌入式平台的開發。本計畫預計完成低複雜度EEG-ICA晶片架構設計、低複雜度EKG-HRV晶片架構設計、低複雜度可適性影像補插晶片等主要生醫晶片/矽置產、低複雜度3D顯示演算法與晶片，並且結合上述晶片與CIC合作開發的生醫嵌入式平台，達成可攜式與即時EEG/EKG/fNIRS生醫訊號擷取展示的目的。未來三年之執行摘要如下所述： 第一年計畫摘要： 第一年的計畫預計將整個系統平台中的EEG-ICA晶片架構設計、EKG-HRV晶片架構設計、可適性影像補插晶片等主要晶片以低複雜度的方式來完成，首先訂定生醫訊號運算之EEG-ICA、EKG-HRV的規格，而設計的重點將會以降低整體演算法複雜度以及晶片面積最小化為主，並在Concord平台上以FPGA驗證其功能正確性，另一方面，在後端顯示平台上，將會先開發低複雜度3D演算法，為了降低3D演算法所需的記憶體，會在前端加入可適性影像補插晶片來降低因為解析度變大而造成的記憶體使用量和運算量，也達到初步低複雜度的生醫運算引擎與平台的建置。 第二年計畫摘要： 第二年的工作預計將第一年的生醫訊號處理EEG、HRV晶片以可重組化的方式來實現，其目的除了將來能做可調式通道數的多功能晶片之外，也可增加系統單晶片(SOC)的整合度，此外，也將低複雜度3D演算法設計實現為晶片，實現成晶片的目的是讓整體生醫嵌入式系統平台的開發更完整，並朝向將Concord平台客製化發展且同時開始著手於各個IP/單元之間的溝通，因為IP/單元之間有效的溝通可以讓整體平台之效能更好，而本年度的持續工作將以完整的生醫運算引擎平台做為目的，並分析結果進行微調，最後，評估系統功能性與穩定性是否符合當初制定的規格。 第三年計畫摘要： 第三年的工作除了持續進行整體系統進一步的整合工作之外，也各別對可重組化的EEG、HRV處理晶片、可適性影像補插晶片和低複雜度3D醫學影像顯示晶片做功耗最佳化的設計，因為在晶片組整合在一起時，有些記憶體及控制器可以共用來降低整體面積及功耗，並進行完整的IP整合與系統測試及驗證，同時將Concord客製化平台與其他子計畫結合展現總計劃當初訂定的規格。

The sub-project 4 referred to as “low complexity biomedical computation engine design and embedded platform development” plays a role of designing the back-end biomedical computation algorithm and chip and the development of back-end 3-D medical graphics display embedded platform. We will concentrate on devising, among three years, low-complexity EEG-ICA, EKG-HRV, adaptive neural-network-based image resizing VLSI architectures and chips. The low-complexity and low power 3D medical graphics algorithm and architecture will be debated in this sub-project. Cooperate with CIC, we will develop biomedical embedded system platform that integrates the above low-complexity computation engines. Finally, one portable and real-time biomedical embedded demo system can be achieved. The executive summary of the next three years is as follows: Abstract of the First Year: The first year of the plan is expected to implement the design of EEG-ICA, EKG-HRV, adaptive neural-network-based image resizing architectures and chips chip architecture using systematic VLSI-signal processing technologies. First, formulate the common specifications of EEG-ICA and EKG-HRV that is wireless connected to the front-end ADC circuit. While, the design focus will be to reduce the overall algorithm complexity and the chip size. Then, we will verify these biomedical computation algorithms by FPGA on CIC-concord platform. On the other hand, at the back-end display platforms, we will develop low-complexity 3-D medical graphics algorithm first. And then, in order to reduce the memory bandwidth requirements and achieve variable resolutions, adaptive NNB image resizing will be adopted. Thus, a primary biomedical embedded system with low-complexity biomedical computation engines can be developed. Abstract of the Second Year: The works of the second year's mission will implement the EEG-ICA and EKG-HRV algorithms in a reconfigurable way for the propose of a multi-function chip with the adjustable channel numbers in the future, and increase the reliability of the system integration. In addition, we implement the first year’s low-complexity 3D algorithm as the chip to integrate with CIC-Concord system. Then, we start to focus on the communications between each IP/component, for the whole platform. The main purpose of this year is to contiguously work for a complete bio-medical computation engine, and analyze the results of the system simulation. Finally, we evaluate the system for its stability and functionality in compliance with the specifications. Abstract of the Third Year: In addition to contiguously carrying on the further integration work of the whole system, the main task of the third year is to optimize the power consumption of the reconfigurable processing chip of ICA and HRV, adaptive image interpolation, and low-complication 3 D medical image accelerator. When the biomedical chips are integrated together, some memories and controllers can be reused to reduce the whole area and power consumption. At last, the customized concord platform will be verified and tested cooperated with other subprojects.