新穎非揮發性奈米點記憶體在薄膜電晶體上的製作與研究

Abstract

近年來，薄膜電晶體(TFT)與奈米點(nanocrystal)的應用技術發展受到相當大的矚目，薄膜電晶體目前廣為液晶顯示器(LCD)產業所大量使用，而奈米點則是可以運用於在非揮發性儲存記憶體上，因其可以解決傳統上利用複晶矽浮停閘(floating gate)做為載子儲存單元的非揮發性記憶體(例如，快閃記憶體)之元件微縮問題，而本計畫將兩者結合起來，並開發新穎結構的非揮發性奈米點記憶體在薄膜電晶體上，其功能可以運用在堆疊式(stacked)的積體電路晶片、軟性電子與省電的攜帶式產品上，對於SOC(System on Chip)的開發與研究提供一個新的元件結構。 複晶矽薄膜電晶體可以在低溫下成長，對於後段製程的熱預算(thermal budget)可以有效的降低，而與奈米點結合，則可以成為新結構的記憶體元件，本計畫即利用先前的薄膜電晶體與奈米點的製作成果技術相互結合來研究此元件的特性，第一年著重於大尺寸的新穎非揮發性奈米點記憶體在薄膜電晶體上的製作與基本電性驗證，利用先前的薄膜電晶體技術與各種不同的奈米點結合(Si、Ge、NiSi、W)，並探討半導體與金屬這些不同材料特性會對非揮發性記憶體有何影響，第二年則進而會改變元件結構，利用多重通道與多重閘極，來研究新穎奈米點記憶體的寫入與抹除效應是否會提升其元件速度，且當元件通道結構微縮至奈米尺度時，邊角效應(corner effect)與奈米點的量子效應則會如何主導我們的薄膜電晶體的開關特性，是本計畫要釐清的重點之一。第三年則是著重於已製備完成的元件記憶體特性量測，本實驗團隊將進行記憶體的可靠度分析，不僅進行DC與AC的加壓量測複晶矽薄膜電晶體元件，並改變環境溫度探討儲存載子的活化能影響及儲存效率，對於容忍度(endurance)與保存能力(retention)也將深入測試，藉此製作一個高效能的非揮發性奈米點結合薄膜電晶體的記憶體元件，以確保有機會可以運用在SOC開發上與其他省電的產品上。

In recent years, the fundamental researches on nanocrystal and thin film transistor have received increasing attentions for the novel technology applications. Thin film transistors (TFTs) are widely used at present in the industry of the liquid crystal display (LCD). In addition, it is well known that nanocrystalline dots can be applied to the nonvolatile electrically erasable programmable read-only memory (EEPROM). Nanocrystal nonvolatile memory (Nanocrystal NVMs) can solve the problems of non-scaling down in traditionally floating gate (FG) nonvolatile memory for highly doped continuous poly-silicon as charge trapping layer. Therefore, the novel device which combined TFTs and Nanocrystal NVMs is proposed in the project. This project is focusd on the development of the novel structure which combines the nonvolatile nanocrystalline dots memory with thin film transistors which can be applied on stacked IC chips, on power-saving portable products, and it also can contribute to the development and research of system on chip (SOC). TFTs fabricated under lower temperature can effectively reduce the thermal budget in the back-end process steps. The device based on TFTs structure with nanocrystals embedded can be also applied for nonvolatile memory. In the first year, the fabrications of thin film transistors combined with different materials nanocrystalline dots (Si、Ge、NiSi、W) is the main topic. The effects of different charge trapping layers on nonvolatile memory will be investigated by using different materials nanocrystal. The TFTs with nano-scale multi-channel and multi-gate will be utilized in the second year. The memory characteristics, such as programming speed, of different device dimension will be inveisgated by the introduction of the structure of multiple channels combined with multiple gate electrodes. Especially, when the devices are shrinking into nanometer scale, the corner effect of multi-channels TFT with nanocrystals will dominate the program/erase characteristics. Furthermore, the quantum effect will be occured obviously. The behavior of write and erase in nano-scaled structure will be studied. Also, the coner effect will be discussed. In the third year, the completely electrical measurement of the fabricated device will be finished, including the reliability under DC and AC stress conditions, the activation energy, charge storage efficiency under varying temperature environments, and the endurance and the retention. By the way, the novel high performance TFTs combined nonvolatile nanocrystals memory will be potential for the application on power-saving portable products, and development of SOC.