高介電材料結合SONOS 之新穎非揮發性記憶體元件製作與物理特性研究(I)

Abstract

近年來，傳統的浮動閘極非揮發性記憶體結構，在隨著元件微縮化、穿隧氧化層隨 縮， 勢必面臨到資料保存上的挑戰。因而透過氧化矽- 氮化矽- 氧化矽 (oxide-nitride-oxide,ONO)及利用量子奈米點作為儲存層相繼被提出，這兩種結構被認 為是非揮發性記憶體元件下一個世代，其中SONOS 結構是利用氮化矽取代浮動閘極作 為記憶體元件之儲存層，利用氮化矽中的缺陷作為隔絕性的儲存中心，改善浮動閘極 微縮後資料容易因為穿隧氧化層劣化而遺失，以解決資料無法長時間保存的問題。 本計畫中，我們將針對現今的SONOS 結構做進一步的提昇並進行物理機制上的討 論。在第一年，我們將透過改變不同材料，利用高介電係數材料取代傳統二氧化矽作 為穿隧氧化層、阻障氧化層或是儲存層，除了建立完整的高介電係數材料薄膜沉積資 料庫外，並透過對元件做完整之電性研究，討論其材料改變所造成的影響，以建立完 整的物理模型釐清載子儲存機制及傳輸原理，希望透過改變材料得到提升傳統SONOS 元件結構的效能。在第二年，我們將著重於記憶體元件的完整製作，透過改變傳統的 MOSFET 結構，如利用奈米線通道等方式，以期能夠提升SONOS 記憶體元件的寫入 抹除效率，也透過完整的電性量測，萃取相關的特性分析，如缺陷密度等。

In recent year, the traditional floating gate memory devices face a challenge about data retention with the device size scaling down and tunneling oxide thinning. Hence, using the oxide-nitride-oxide (ONO) and the nanodots structure to be the trapping layer was proposed sequentially. These structures are thought to be the next generation of the nonvolatile memory devices. The silicon-oxide-nitride-oxide-silicon (SONOS) memory devices store the data by trap the charges in the trap-rich nitride. The stored charges are not lost because the isolation of the trapping sites in nitride. Even if the tunneling oxide is degraded, the data retention is improved. In this project, we will enhance the performance of the SONOS devices and discuss the physical models of the data storage. In the first year of the project, we will replace silicon oxide with the high-k materials to be the tunneling oxide, blocking oxide or trapping layer. Besides establishing the data base of the deposited high-k thin films, the electrical effects of high-k materials will also be studied using CV, IV and DLTS technology of measurement. In addition, the whole physical models of charge trapping and the mechanisms of carriers transport will be defined to enhance the performance of SONOS memory devices. In the second year of the project, we will focus on the whole fabrication of the Metal-Oxide-Silicon Field Effect Transistor(MOSFET) structure. The program and erase efficiency will be improved by the changes of the device structure such as use the nanowires to be the channel of the device. Additionally, we also extract the electrical characteristics of the memory devices through whole electrical measurement.