標題: 嵌入式網路通訊裝置評比技術與工具之研發---子計畫四:嵌入式網路通訊裝置儲存裝置效能評比基準與工具之研發
Design and Development of Benchmarking Technologies and Tools for Storage Systems of Embedded Network and Communication Devices
作者: 張立平
Chang Li-Pin
國立交通大學資訊工程學系(所)
關鍵字: 效能評比;固態硬碟;快閃記憶體;檔案系統;嵌入式系統;作業系統;Benchmark;solid-state disks;flash memory;file system;embedded system;operating system
公開日期: 2008
摘要: 由於快閃記憶體的良好物理特性,如非揮發性,耐震,以及省電,使得它一向是嵌 入式系統中儲存媒體的最好選擇。作為一個儲存媒體,目前評比快閃記憶體為基礎 的儲存系統效能的方法,還是援用設計給以磁碟為基礎之儲存系統的既有方法。這 些方法固然可以測出一些表面的效能瓶頸,但是卻無法深入發掘導致效能低落的問 題所在,而這些問題往往是與快閃記憶體的特殊管理議題有關。舉例來說,快閃記 憶體上面的可用空間是由垃圾回收方法所產生的,這種內部動作,會不時產生冗長 的停頓時間。而垃圾回收則會磨損快閃記憶體。而為了平均地磨損快閃記憶體,又 有了平均磨損的議題。因此,除了典型之回應時間與資料吞吐量,欲佈署快閃記憶 體在嵌入式系統中以為儲存媒體,測試評比之對象,還必須包含快閃記憶體的壽命 問題,即時應用程式支援能力,時間以及空間計算資源之成本,快閃記憶體的空間 利用率,快閃記憶體傳輸介面之頻寬利用率等等。 本研究計畫的目的,在於針對快閃記憶體為基礎之儲存系統,設計與實作出完整之 效能評比程序,工具,以及技術。測試對象有二:快閃記憶體檔案系統,以及固態 硬碟。工作項目包括:作業系統核心與韌體之事件擷取機制,標準測試程序之建立, 測試標竿之設計,完整之批次測試工具,以及虛擬平台技術。本計畫進行分為三年: 第一年,針對既有方法與產品,做大規模並正規之效能評比。產出之效能評比結果, 除了瞭解不同待測物各自的優勢,最重要的議題是能定論何種待測物不適用於哪一 種應用系統。而測試評比之經驗,則可延伸至測試工具的設計與實作。第二年,基 於第一年之經驗,設計出批次測試評比之相關工具。此外,基於批次測試技術,我 們的技術議題則延伸至自動診斷技術,用以發現待測物的效能瓶頸與弱點。本年度 為達成可接受待測物並且進行in-lab測試。第三年則延續第二年開發之工具與技術, 產出可逕付廠商之測試工具與測試程序。而為了進行快速測試與驗證,本年度的技 術議題則為虛擬平台。虛擬平台技術是將快閃記憶體管理軟體與外界之所有介面做 一個行為的抽象。有了虛擬平台,廠商不必將待測物之源碼開放給測試實驗室,便 可搭配測試評比工具,逕行對快閃記憶體之管理方法作白箱測試以及與反覆的修改 與驗證。
Flash memory is widely deployed in embedded computing systems because of its non-volatility, shock-resistance, and power conservation. To test the performance of flash-memory-based storage systems, currently benchmark suites for disk-based storage systems are used. The ordinary benchmark suites may identify the commonly existing performance bottleneck, the source that causes the performance degradation is not easy to identify, though. That is because the physical characteristics and geometry of flash memory impose many constraints on its management. For example, newly written data are dispatched to garbage-collected space. Garbage collection would involve intensive internal data movement and then introduce lengthy delay. Furthermore, garbage collection would wear portions of the flash memory out. So to lengthen the overall lifespan of flash memory, wear-leveling activities would then be performed. By the above discussions we may found that to test a flash-memory-based storage system is very different from to test a disk-based ones. Besides response and throughput, to test flash-memory-based embedded storage systems we have to include the lifetime issue, the support of real-time applications, the computational-resource costs of time and space, flash-memory space utilization, and bandwidth utilization. The objective of this research project is to design and implement the tools, procedures and methods of benchmark for flash-memory-based storage systems. Working items include the methods to capture and to analyze kernel/firmware events, design of test procedures and performance indexes, implementation of batch test tools, and platform-surrogating techniques. In the first year, we would conduct large-scale benchmark on existing flash-memory file systems and storage systems. The technique issue is not only to find under what circumstances a storage system would deliver good performance but also to reveal that under what workloads the storage system would performs poorly. In the second year, in-lab benchmark tools and procedures are to be completed. A technical item is to develop an auto-pilot diagnosing procedure. It is to automatically target and to identify the design weak points pertaining to performance degradation. In the third year, complete test tools and procedures can be delivered to vendors so that they can independently test their products without much consulting us. To speed up the test and benchmark, a technique referred to as platform surrogating is to be developed. It is to provide abstraction model of hardware and related software interface. With platform surrogating, vendors may transfer their firmware/driver source code to the virtual platform without many modifications. By jointly using the benchmark tools and the platform-surrogating technique, the cycle of test, debug, and benchmark of their algorithms can be significantly accelerated.
官方說明文件#: NSC97-2218-E009-035
URI: http://hdl.handle.net/11536/102873
https://www.grb.gov.tw/search/planDetail?id=1697491&docId=293360
顯示於類別:研究計畫