Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 李毅郎 | en_US |
dc.contributor.author | Li Yih-Lang | en_US |
dc.date.accessioned | 2014-12-13T10:51:50Z | - |
dc.date.available | 2014-12-13T10:51:50Z | - |
dc.date.issued | 2007 | en_US |
dc.identifier.govdoc | NSC96-2220-E009-011 | zh_TW |
dc.identifier.uri | http://hdl.handle.net/11536/102932 | - |
dc.identifier.uri | https://www.grb.gov.tw/search/planDetail?id=1463757&docId=262332 | en_US |
dc.description.sponsorship | 行政院國家科學委員會 | zh_TW |
dc.language.iso | zh_TW | en_US |
dc.title | 單晶片系統驗證之核心技術開發---子計畫五:系統晶片布局設計後之驗證與最佳化平台研究(III) | zh_TW |
dc.title | Post-Layout Verification and Optimization Platform(III) | en_US |
dc.type | Plan | en_US |
dc.contributor.department | 國立交通大學資訊工程學系(所) | zh_TW |
Appears in Collections: | Research Plans |