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dc.contributor.author鄭裕庭en_US
dc.contributor.author趙子元en_US
dc.contributor.author許名伽en_US
dc.contributor.author陳智en_US
dc.contributor.author劉健民en_US
dc.date.accessioned2014-12-16T06:12:28Z-
dc.date.available2014-12-16T06:12:28Z-
dc.date.issued2011-03-01en_US
dc.identifier.govdocG06K019/07zh_TW
dc.identifier.govdocH01F017/04zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/103641-
dc.description.abstract本發明係有關於一種晶片電感結構及其製造方法,其包含一基板、一多孔層、複數導體與一電感,多孔層設置於基板上方且有複數孔洞,該些導體分別設於該些孔洞,電感設置於多孔層上方。本發明藉由該些導體作為核心,如此可增加電感值,且可縮小晶片電感的面積,並降低生產成本,此外本發明之製造方法簡單,且相容於CMOS製程,而可降低生產成本。zh_TW
dc.language.isozh_TWen_US
dc.title晶片電感結構及其製造方法zh_TW
dc.typePatentsen_US
dc.citation.patentcountryTWNzh_TW
dc.citation.patentnumber201108120zh_TW
Appears in Collections:Patents


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