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dc.contributor.authorChen, Jung-Shengen_US
dc.contributor.authorKer, Ming-Douen_US
dc.date.accessioned2014-12-08T15:13:26Z-
dc.date.available2014-12-08T15:13:26Z-
dc.date.issued2007-09-01en_US
dc.identifier.issn1551-319Xen_US
dc.identifier.urihttp://dx.doi.org/10.1109/JDT.2007.900916en_US
dc.identifier.urihttp://hdl.handle.net/11536/10380-
dc.description.abstractA new proposed gate-bias voltage-generating technique with threshold-voltage compensation for analog circuits in the low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) is proposed. The new proposed gate-bias voltage-generating circuit with threshold-voltage compensation has been successfully verified in an 8-mu m LTPS process. The experimental results have shown that the impact of TFT threshold-voltage variation on the biasing circuit can be reduced from 30% to 5% under a biasing voltage of 3 V. The new proposed gate-bias voltage-generating technique with thresh old-voltage compensation enables the analog circuits to be integrated and implemented by the UPS process on glass substrate for an active matrix LCD panel.en_US
dc.language.isoen_USen_US
dc.subjectanalog circuiten_US
dc.subjectbiasing circuiten_US
dc.subjectlow-temperature polycrystalline silicon (LTPS)en_US
dc.subjectthin-film transistor (TFT)en_US
dc.subjectthreshold-voltage compensationen_US
dc.subjectthreshold-voltage variationen_US
dc.titleNew gate-bias voltage-generating technique with threshold-voltage compensation for on-glass analog circuits in LTPS processen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/JDT.2007.900916en_US
dc.identifier.journalJOURNAL OF DISPLAY TECHNOLOGYen_US
dc.citation.volume3en_US
dc.citation.issue3en_US
dc.citation.spage309en_US
dc.citation.epage314en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000259064500011-
dc.citation.woscount9-
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