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dc.contributor.author朱燁霖en_US
dc.contributor.author黃威en_US
dc.date.accessioned2014-12-16T06:13:22Z-
dc.date.available2014-12-16T06:13:22Z-
dc.date.issued2007-05-01en_US
dc.identifier.govdocG11C011/4063zh_TW
dc.identifier.govdocG06F005/10zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/104094-
dc.description.abstract本發明提供一種非同步先進先出暫存器單元(Asynchronous First-In-First-Out Cell),運用修改過的Muller C元件使非同步先進先出暫存器單元之電路複雜程度降低,其不但具有重複使用的特性,並能在不同頻率下之不同的供應電壓或單一供應電壓下操作。此外,應用在以全域非同步局部同步系統為根基,雙電壓系統十六點的radix-2^2之快速傅利葉轉換架構的介面電路上,發現能減少較多的功率損耗與降低更多的延遲時間。zh_TW
dc.language.isozh_TWen_US
dc.title非同步先進先出暫存器單元zh_TW
dc.typePatentsen_US
dc.citation.patentcountryTWNzh_TW
dc.citation.patentnumber200717519zh_TW
Appears in Collections:Patents


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