Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee Shuenn-Gi | en_US |
dc.contributor.author | Wang Chung Hsuan | en_US |
dc.contributor.author | Sheen Wern-Ho | en_US |
dc.date.accessioned | 2014-12-16T06:14:01Z | - |
dc.date.available | 2014-12-16T06:14:01Z | - |
dc.date.issued | 2013-06-18 | en_US |
dc.identifier.govdoc | G11C029/00 | zh_TW |
dc.identifier.govdoc | G01R031/28 | zh_TW |
dc.identifier.govdoc | G06F011/00 | zh_TW |
dc.identifier.govdoc | G06F012/00 | zh_TW |
dc.identifier.govdoc | G06F013/00 | zh_TW |
dc.identifier.govdoc | G06F013/28 | zh_TW |
dc.identifier.uri | http://hdl.handle.net/11536/104472 | - |
dc.description.abstract | An address generation apparatus for quadratic permutation polynomial (QPP) interleaver receives several configurable parameters and uses a plurality of QPP units to compute and outputs a plurality of interleaving addresses according to a QPP function Π(i)=(f1i+f2i2) mod k, where f1 and f2 are QPP coefficients, k is information block length of an input sequence, 0≦i≦k−1, and mod is a modulus operation. Each of the plurality of QPP units is a parallel computation unit, and outputs in parallel a corresponding group of interleaver addresses, where Π(i) is also a ith interleaving address generated by the apparatus. | zh_TW |
dc.language.iso | zh_TW | en_US |
dc.title | Address generation apparatus and method for quadratic permutation polynomial interleaver | zh_TW |
dc.type | Patents | en_US |
dc.citation.patentcountry | USA | zh_TW |
dc.citation.patentnumber | 08468410 | zh_TW |
Appears in Collections: | Patents |
Files in This Item:
If it is a zip file, please download the file and unzip it, then open index.html in a browser to view the full text content.