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dc.contributor.authorLee Shuenn-Gien_US
dc.contributor.authorWang Chung Hsuanen_US
dc.contributor.authorSheen Wern-Hoen_US
dc.date.accessioned2014-12-16T06:14:01Z-
dc.date.available2014-12-16T06:14:01Z-
dc.date.issued2013-06-18en_US
dc.identifier.govdocG11C029/00zh_TW
dc.identifier.govdocG01R031/28zh_TW
dc.identifier.govdocG06F011/00zh_TW
dc.identifier.govdocG06F012/00zh_TW
dc.identifier.govdocG06F013/00zh_TW
dc.identifier.govdocG06F013/28zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/104472-
dc.description.abstractAn address generation apparatus for quadratic permutation polynomial (QPP) interleaver receives several configurable parameters and uses a plurality of QPP units to compute and outputs a plurality of interleaving addresses according to a QPP function Π(i)=(f1i+f2i2) mod k, where f1 and f2 are QPP coefficients, k is information block length of an input sequence, 0≦i≦k−1, and mod is a modulus operation. Each of the plurality of QPP units is a parallel computation unit, and outputs in parallel a corresponding group of interleaver addresses, where Π(i) is also a ith interleaving address generated by the apparatus.zh_TW
dc.language.isozh_TWen_US
dc.titleAddress generation apparatus and method for quadratic permutation polynomial interleaverzh_TW
dc.typePatentsen_US
dc.citation.patentcountryUSAzh_TW
dc.citation.patentnumber08468410zh_TW
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