Pin-out designation method for package-board codesign

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Lee Ren-Jie	en_US
dc.contributor.author	Chen Hung-Ming	en_US
dc.date.accessioned	2014-12-16T06:14:09Z	-
dc.date.available	2014-12-16T06:14:09Z	-
dc.date.issued	2012-10-30	en_US
dc.identifier.govdoc	G06F017/50	zh_TW
dc.identifier.uri	http://hdl.handle.net/11536/104534	-
dc.description.abstract	A pin out designation method for package board codesign has steps of defining pin characteristics and requirements, generating multiple pin patterns, pin blocks construction and grouping and pin blocks floorplanning. Designers may use an EDA tool to generate multiple pin patterns and may use the pin patterns to construct multiple pin blocks, to group the pin blocks around four sides of a chip and to adjust the pin blocks into a minimized package size of the chip.	zh_TW
dc.language.iso	zh_TW	en_US
dc.title	Pin-out designation method for package-board codesign	zh_TW
dc.type	Patents	en_US
dc.citation.patentcountry	USA	zh_TW
dc.citation.patentnumber	08302067	zh_TW
顯示於類別：	專利資料

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