完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Hsieh Chung-Ying | en_US |
dc.contributor.author | Chang Ming-Hung | en_US |
dc.contributor.author | Hwang Wei | en_US |
dc.date.accessioned | 2014-12-16T06:14:12Z | - |
dc.date.available | 2014-12-16T06:14:12Z | - |
dc.date.issued | 2012-08-07 | en_US |
dc.identifier.govdoc | H03L007/06 | zh_TW |
dc.identifier.govdoc | H03L007/00 | zh_TW |
dc.identifier.uri | http://hdl.handle.net/11536/104560 | - |
dc.description.abstract | A programmable clock generator, which is used in dynamic-voltage-and-frequency-scaling (DVFS) operated in Sub- and Near-Threshold region. The programmable clock generator includes first pulse generating unit and a pulse multiplier. A first counter is configured to generate a first counting signal, so as to control the phase detector comparing the phase difference between a first pulse signal and a second pulse signal. A first control signal is transmitted by a control unit in accordance with a phase difference signal, and the phase of the second pulse signal is adjusted by a lock-in delay unit, so that a predetermined phase is generated between the first pulse signal and the second pulse signal. The PVT variation may be compensated by the programmable clock generator during the sub threshold region. Therefore, the period of reference clock is in the locking range of lock-in delay line. | zh_TW |
dc.language.iso | zh_TW | en_US |
dc.title | Programmable clock generator used in dynamic-voltage-and-frequency-scaling (DVFS) operated in sub- and near- threshold region | zh_TW |
dc.type | Patents | en_US |
dc.citation.patentcountry | USA | zh_TW |
dc.citation.patentnumber | 08237477 | zh_TW |
顯示於類別: | 專利資料 |