完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chen Wei Zen | en_US |
dc.contributor.author | Lee Yen-Wei | en_US |
dc.date.accessioned | 2014-12-16T06:14:14Z | - |
dc.date.available | 2014-12-16T06:14:14Z | - |
dc.date.issued | 2012-05-22 | en_US |
dc.identifier.govdoc | H03D003/24 | zh_TW |
dc.identifier.govdoc | H03L007/00 | zh_TW |
dc.identifier.govdoc | H03M003/00 | zh_TW |
dc.identifier.uri | http://hdl.handle.net/11536/104579 | - |
dc.description.abstract | A phase-locked loop frequency synthesizer and a loop locking method thereof are provided. The phase-locked loop frequency synthesizer includes a reference route sigma-delta modulator feedback circuit, a reference phase integration circuit coupled to the output end of the reference route sigma-delta modulator feedback circuit, a phase/frequency detector coupled to the output ends of the reference and feedback phase integration circuit, a loop filter coupled to the output end of the phase/frequency detector and the input end of the reference route sigma-delta modulator feedback circuit, an oscillator coupled to the output end of the loop filter, and a feedback phase integration circuit coupled to the output end of the oscillator and the input end of the phase/frequency detector. In the phase-locked loop frequency synthesizer, the oscillator generates corresponding frequency output signals which yield the advantages of resisting noise signals, enhancing resolution, and facilitating integration. | zh_TW |
dc.language.iso | zh_TW | en_US |
dc.title | Phase-locked loop frequency synthesizer and loop locking method thereof | zh_TW |
dc.type | Patents | en_US |
dc.citation.patentcountry | USA | zh_TW |
dc.citation.patentnumber | 08183936 | zh_TW |
顯示於類別: | 專利資料 |