行動無線通訊使用之快速切換頻率合成器

Abstract

近幾年來，由於個人行動通訊服務的快速成長，而行動無線通訊的一些問 題也就突顯出來。在高頻電路設計中，其所包含的關鍵性零組件–頻率合 成器也伴隨著而有更快速、更省電以及更高頻率的需求。本文將從傳統的 單一迴路鎖相電路之頻率合成器討論起，之後，回顧近二十年來為了增快 其頻率切換速度所衍生出來的技術。其次，再針對頻率檢測器輔助鎖相電 路技術作進一步的探討。最後，介紹一種利用數位適應性增量調變技術， 應用於頻率截獲過程，以達快速切換頻率之需求。此外，在本文之中提供 了一些從工程應用觀點上的設計經驗準則，以及設計快速頻率合成器的考 慮點。同時，在最後一章，亦提供了一些未來發展頻率合成器仍待改進的 相關技術。 As personal communication service (PCS) rapidly grows up, system and circuit design problems for mobile radio communications are overwhelming studied in recent years. In RF design, the key components, frequency synthesizers, must have faster speed, lower power, and higher operation frequency requirements. This thesis begins with a discussion of the conventional single-loop PLL synthesizer. In the following, we review the fast switching techniques that have been developed in the last two decades. Moreover, the frequency detector aided PLL synthesizer will be further explored. Finally, we introduce a method which uses the digital adaptive delta modulation technique in the frequency acquisition process in order to improve the fast switching speed requirements. In additional, we present some design rules from viewpoints of engineering experience for designing fast switching frequency synthesizers. In the last chapter, we also provide technical directions for improving frequency synthesizer switching speed in the future.