應用於IEEE802.11a之低功耗頻率合成器

Abstract

本論文分為三大部分，第一部份介紹目前的無線通訊發展並描述研究的動機，並且針對IEEE 802.11a WLAN接收機系統作規畫，詳細整理現今IEEE 802.11a系統的規範與設計規格，最後介紹相位雜訊對於訊號的影響。 論文第二部分採用TSMC 0.18 μm製程，設計應用於IEEE 802.11a的LC電壓控制振盪器，主要強調低功耗、低相位雜訊，並且可使用於第三部分的頻率合成器之中。論文最後部分採用TSMC 0.18 μm製程，設計應用於IEEE 802.11a之整數型頻率合成器，主要強調低功耗、整合性高以及快速鎖定，架構包括相位頻率偵測器(PFD)、電荷幫浦(CP)、壓控振盪器(VCO)、除頻器(DIVIDER)以及迴路濾波器(LP)。 本論文一共分為四章：第一章緒論，第二章為LC電壓控制振盪器的原理、設計與量測結果，得到低功耗低雜訊的表現，第三章則為頻率合成器理論、設計與量測結果，在18mW的功率消耗下獲得低雜訊的表現，最後，第四章提出結論與未來展望。

This thesis consists of three parts. Part I illustrates the current and future developments of wireless communication and depicts the motivation. Furthermore, we also demonstrate the system planning and system specification for IEEE 802.11a. Part 2 of this thesis shows GM boost technique voltage-controlled oscillator (VCO) which are applied in IEEE 802.11a. The VCO proposed in this thesis featured low power and low phase noise. All the proposed circuits were implemented and designed in TSMC 0.18μm mixed-signal/RF CMOS technology. Finally, Part 3 proposes the frequency synthesizer which is designed for IEEE 802.11a including phase frequency detector (PFD), charge pump (CP), voltage-controlled oscillator (VCO), divider and loop filter (LF). The frequency synthesizer proposed in this thesis featured low power, highly integrated and fast locking. This thesis is divided into four chapter, including introduction, design of the voltage controll oscillator and the frequency synthesizer, discussion and future work.