適用於802.11a無線區域網路之頻率合成器設計

Abstract

本論文完成一適用於IEEE 802.11a之頻率合成器設計，並以聯電0.18微米製程實現，整個頻率合成器是基於電荷泵鎖相迴路，並使用整數除頻架構來達到頻率合成的目的，其中包含了壓控振盪器、除頻器、相位偵測器、電荷泵和晶片外之二階迴路濾波器。壓控振盪器本身之輸出頻率位於5-GHz，因此在壓控振盪器與除頻器之間加入一高頻的除2電路來降低預除器的設計及功率消耗。壓控振盪器本身所量測到的可調範圍從5.15-GHz到5.45-GHz，相位雜訊在100-kHz的偏移量為-69 dBc/Hz和在1-MHz的偏移量為-89 dBc/Hz，而此壓控振盪器在1.8-V供應電壓下所消耗的功率為15 mW。另外，高頻的除2電路量測到的輸入操作頻率從2.8-GHz到6.2-GHz，而所消耗的功率為4.5 mW。整個頻率合成器採用矽品所提供之QFN系列包裝，並以RO40003版材所製作之印刷電路板做為量測模組。

A 5-GHz IEEE 802.11a frequency synthesizer has been fabricated in UMC 0.18-μm CMOS technology. The frequency synthesizer architecture is based on a charge-pump phase-locked loop. To perform frequency synthesis, the synthesizer utilizes the integer-N architecture. It consists of VCO, frequency divider, phase/frequency detector, charge pump, and an off-chip 2rd passive loop filter. Because the oscillation frequency of the VCO is at 5-GHz, a high frequency divide-by-two circuit is inserted between the VCO and the pulse-swallow divider to relax the operation of the prescaler. The measured VCO performance has a frequency range from 5.15-GHz to 5.45-GHz. The phase noise is -69 dBc/Hz at 100-kHz frequency offset and -83 dBc/Hz at 1-MHz frequency offset. The VCO consumes 15 mW from 1.8-V supply including the output buffers. The measured input operating frequency of the high-frequency divide-by-two circuit is from 2.8-GHz to 6.2-GHz. It draws 4.5 mW from 1.8-V supply. The synthesizer has been packaged in QFN-20 provided by SPIL and mounted on a RO40003 board.