IEEE 802.11a 四相位頻率合成器

Abstract

本論文第一章針對目前的無線通訊發展作簡介並描述研究的動機與想法,第二章針對選定IEEE 802.11a WLAN接收機系統作規畫,首先介紹相位雜訊對於訊號的影響,推得接收機的振盪器相位雜訊要求至少為-90 dBc/Hz(@100 KHz),鎖定時間必需小於256 μs。 論文第二部分採用 TSMC 0.18 μm製成,設計應用於IEEE 802.11a 之四相位整數型頻率合成器,包括相位頻率偵測器(PFD)、電荷幫補(CP)、四相位壓控振盪器(QVCO)以及迴路濾波器(LP)。其中QVCO加入開關切換開關電容來達到寬頻帶的設計以應變製程所造成的變化。此外在除頻器的部分採用可調整除數之除頻器來達到寬除頻數的結果,所有類比數位電路操作電壓為1.8 V。 本論文一共分五章:第一章緒論、第二章為頻率合成器系統規畫、第三章為頻率合成器理論,第四章為頻率合成器的各子電路介紹、第四章為各級電路操作原理與設計、第五章為模擬與量測結果、第六章為結論與未來展望。

This thesis is applied for IEEE 802.11a, chapter 1 illustrate the current and future developments of wireless communication, and depicts the motivation. In chapter 2, before design the circuit, the system planning is needed, because the phase noise of oscillator will degrade the system performance, thus, form system specification we can calculate the phase noise of the VCO should reach -90 dBc/Hz@100KHz, and the settling time of the PLL must not exceed 256 μs. In the part 2 of this thesis, the quadrature frequency synthesizer is designed for IEEE 802.11a including phase frequency detector (PFD), charge pump (CP), quadrature voltage control oscillator (QVCO) and loop filter (LP). A swiching capacitor is added into QVCO to prevent it from the process variation, and a multi-modulus divider is selected to reach the specification of the system. Furthermore, all of the analog and digital circuit use 1.8 V. This thesis is divide into five chapter, chpter 1 is introduction and the motivation, chapter 2 is the system planning, chapter 3 is the theory of the synthesizer, chapter 4 is the sub-circuits of the synthesizer, chapter 5 is the simulation and measurment and chapter 6 is the discussion and the future work.