Staggered source/drain and thin-channel TFT structure and fabrication method thereof

Abstract

This invention relates to a process for fabricating a staggered source/drain and thin-channel TFT structure, which simplifies the conventional process for fabricating the structure by decreasing the number of mask steps and achieving better results at suppressing the electric field near the drain junction and reducing the leakage current. The process comprises (1) re-crystallizing a-Si into poly-Si (02), which is performed by depositing an a-Si layer on a substrate and then applying a general photolithographic step and a RIE etching step for defining the amorphous Si islands provided with higher regions and lower regions, wherein the residual width of the thin channel of the a-Si is about 5 to 200 nm after etching; then the a-Si is changed into poly-Si (02) after a subsequent annealing; (2) defining the gate region (05), source/drain region (07) and the channel; (3) applying the implantation; and (4) applying the connection.