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dc.contributor.authorWuen_US
dc.contributor.authorJieh-Tsorngen_US
dc.contributor.authorWangen_US
dc.contributor.authorTa-Huien_US
dc.contributor.authorChangen_US
dc.contributor.authorHsie-Chiaen_US
dc.date.accessioned2014-12-16T06:14:31Z-
dc.date.available2014-12-16T06:14:31Z-
dc.date.issued2007-07-10en_US
dc.identifier.govdocG11C029/00zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/104789-
dc.description.abstractA memory combines plural memory cells for storing data wherein the differential stages voltage levels of memory cells are not limited in square value of 2 and can be improved linearly. The feature of the present invention can also increase memory capacity without increasing memory area. Furthermore it can remain voltage levels which cannot express 0 and 1 combination for error erasure messages when data is read. For efficient usage of memory, the increased memory capacity is not only for storing data but also for storing error correction scheme to assure the veracity of the storing data and improve producing yield and reliability for multilevel memory systems.zh_TW
dc.language.isozh_TWen_US
dc.titleMethod of combining multilevel memory cells for an error correction schemezh_TW
dc.typePatentsen_US
dc.citation.patentcountryUSAzh_TW
dc.citation.patentnumber07243277zh_TW
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