標題: | Cyclic redundancy check modification for message length detection and error detection |
作者: | Shien Shin-Lin |
公開日期: | 3-Jul-2007 |
摘要: | In a method for a variable-length communications system including encoding a message and decoding a data bit stream, the message includes a plurality of message blocks. A message block of the message is encoded by generating a parity check bit stream, flipping the parity check bit stream, and appending the flipped parity check bit stream to the end of the message block. When a data bit stream is received, a guessed message block and a guessed flipped parity check bit stream are extracted based on a guessed message block length. A parity check bit stream is generated for the guessed message block and then flipped. If the flipped parity check bit stream is the same as the guessed flipped parity check bit stream, the message block has been identified. Otherwise, the guessed message block length is increased by 1 and the above step is repeated. |
官方說明文件#: | H03M013/00 |
URI: | http://hdl.handle.net/11536/104791 |
專利國: | USA |
專利號碼: | 07240273 |
Appears in Collections: | Patents |
Files in This Item:
If it is a zip file, please download the file and unzip it, then open index.html in a browser to view the full text content.