完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | HWANG Wei | en_US |
dc.contributor.author | WANG Dao-Ping | en_US |
dc.date.accessioned | 2014-12-16T06:14:46Z | - |
dc.date.available | 2014-12-16T06:14:46Z | - |
dc.date.issued | 2014-07-17 | en_US |
dc.identifier.govdoc | G11C011/412 | zh_TW |
dc.identifier.uri | http://hdl.handle.net/11536/104888 | - |
dc.description.abstract | A 10-transistor dual-port SRAM with shared bit-line architecture includes a first memory cell and a second memory cell. The first memory cell has a first storage unit, a first switch set, and a second switch set. The second memory cell has a second storage unit, a third switch set, and a fourth switch set. The second switch set is coupled to a complement first A-port bit line and a complement first B-port bit line, and connected to the first storage unit. The third switch set is connected to a complement second A-port bit line, a complement second B-port bit line, and the second storage unit. Thus, the second memory cell can make use of the third switch set to share the complement first A-port bit line and the complement first B-port bit line with the first memory cell. | zh_TW |
dc.language.iso | zh_TW | en_US |
dc.title | TEN-TRANSISTOR DUAL-PORT SRAM WITH SHARED BIT-LINE ARCHITECTURE | zh_TW |
dc.type | Patents | en_US |
dc.citation.patentcountry | USA | zh_TW |
dc.citation.patentnumber | 20140198562 | zh_TW |
顯示於類別: | 專利資料 |