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dc.contributor.authorCHU Chia-Chingen_US
dc.contributor.authorLIN Yi-Minen_US
dc.contributor.authorYANG Chi-Hengen_US
dc.contributor.authorCHANG Hsie-Chiaen_US
dc.date.accessioned2014-12-16T06:14:49Z-
dc.date.available2014-12-16T06:14:49Z-
dc.date.issued2014-04-03en_US
dc.identifier.govdocG06F011/10zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/104929-
dc.description.abstractA memory system, a fully parallel encoding method, and a fully parallel decoding method are disclosed. The encoding method utilizes a plurality of minimal polynomials that constitute a generator polynomial to derive a plurality of roots from the minimal polynomials. A first encoding matrix derived according to the roots of the minimal polynomials is subsequently decomposed to derive a second encoding matrix, in which partial elements of the second encoding matrix are common in those of a parity check matrix of the decoder, such that the encoder and the decoder can efficiently share the same hardware. In addition, the decoding method defines a new error locator polynomial and utilizes a cubic matrix operation to respectively combine the equations, which reduces the hardware required by the fully parallel architecture.zh_TW
dc.language.isozh_TWen_US
dc.titleFULLY PARALLEL ENCODING METHOD AND FULLY PARALLEL DECODING METHOD OF MEMORY SYSTEMzh_TW
dc.typePatentsen_US
dc.citation.patentcountryUSAzh_TW
dc.citation.patentnumber20140095960zh_TW
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