完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | CHU Chia-Ching | en_US |
dc.contributor.author | LIN Yi-Min | en_US |
dc.contributor.author | YANG Chi-Heng | en_US |
dc.contributor.author | CHANG Hsie-Chia | en_US |
dc.date.accessioned | 2014-12-16T06:14:49Z | - |
dc.date.available | 2014-12-16T06:14:49Z | - |
dc.date.issued | 2014-04-03 | en_US |
dc.identifier.govdoc | G06F011/10 | zh_TW |
dc.identifier.uri | http://hdl.handle.net/11536/104929 | - |
dc.description.abstract | A memory system, a fully parallel encoding method, and a fully parallel decoding method are disclosed. The encoding method utilizes a plurality of minimal polynomials that constitute a generator polynomial to derive a plurality of roots from the minimal polynomials. A first encoding matrix derived according to the roots of the minimal polynomials is subsequently decomposed to derive a second encoding matrix, in which partial elements of the second encoding matrix are common in those of a parity check matrix of the decoder, such that the encoder and the decoder can efficiently share the same hardware. In addition, the decoding method defines a new error locator polynomial and utilizes a cubic matrix operation to respectively combine the equations, which reduces the hardware required by the fully parallel architecture. | zh_TW |
dc.language.iso | zh_TW | en_US |
dc.title | FULLY PARALLEL ENCODING METHOD AND FULLY PARALLEL DECODING METHOD OF MEMORY SYSTEM | zh_TW |
dc.type | Patents | en_US |
dc.citation.patentcountry | USA | zh_TW |
dc.citation.patentnumber | 20140095960 | zh_TW |
顯示於類別: | 專利資料 |