完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | CHEN Tsung-Lin | en_US |
dc.contributor.author | CHANG Edward Yi | en_US |
dc.contributor.author | CHIENG Wei-Hua | en_US |
dc.contributor.author | CHENG Stone | en_US |
dc.contributor.author | JENG Shyr-Long | en_US |
dc.contributor.author | HUANG Shin-Wei | en_US |
dc.date.accessioned | 2014-12-16T06:14:55Z | - |
dc.date.available | 2014-12-16T06:14:55Z | - |
dc.date.issued | 2013-09-19 | en_US |
dc.identifier.govdoc | H03K003/00 | zh_TW |
dc.identifier.uri | http://hdl.handle.net/11536/104995 | - |
dc.description.abstract | The present invention provides a current limit circuit apparatus, coupled with the gate of a GaN transistor. The current limit circuit comprises a diode, a first transistor, a second transistor, a first resistor, a second resistor, a third resistor and a fourth resistor. The source and the drain of the first transistor couple with the diode. The source of the second transistor couples with the gate of the first transistor. The source of the first transistor couples with the first transistor. The source of the second transistor couples with the second resistor. The third resistor couples with the fourth resistor and the gate of the first transistor. The first transistor turned off and the gate current is limited. When the current of the gate of the GaN transistor exceeds the predetermined value, the breakdown voltage is increased by limiting the gate current. | zh_TW |
dc.language.iso | zh_TW | en_US |
dc.title | Current limit circuit apparatus | zh_TW |
dc.type | Patents | en_US |
dc.citation.patentcountry | USA | zh_TW |
dc.citation.patentnumber | 20130241603 | zh_TW |
顯示於類別: | 專利資料 |