ELECTRICAL TEST STRUCTURE APPLYING 3D-ICS BONDING TECHNOLOGY FOR STACKING ERROR MEASUREMENT

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DC 欄位	值	語言
dc.contributor.author	Chen Kuan-Neng	en_US
dc.contributor.author	Li Shih-Wei	en_US
dc.date.accessioned	2014-12-16T06:15:00Z	-
dc.date.available	2014-12-16T06:15:00Z	-
dc.date.issued	2013-03-14	en_US
dc.identifier.govdoc	H01L023/48	zh_TW
dc.identifier.uri	http://hdl.handle.net/11536/105066	-
dc.description.abstract	A 3D integrated circuit including a first wafer and a second wafer is provided. The first wafer includes a first conduction pattern. The second wafer includes a second conduction pattern which is electrically connected to the first conduction pattern. A displacement between the first wafer and the second wafer is determined by a resistance of the first conduction pattern and the second conduction pattern.	zh_TW
dc.language.iso	zh_TW	en_US
dc.title	ELECTRICAL TEST STRUCTURE APPLYING 3D-ICS BONDING TECHNOLOGY FOR STACKING ERROR MEASUREMENT	zh_TW
dc.type	Patents	en_US
dc.citation.patentcountry	USA	zh_TW
dc.citation.patentnumber	20130062776	zh_TW
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