完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | CHANG Yung | en_US |
dc.contributor.author | Huang Po-Tsang | en_US |
dc.contributor.author | Hwang Wei | en_US |
dc.date.accessioned | 2014-12-16T06:15:01Z | - |
dc.date.available | 2014-12-16T06:15:01Z | - |
dc.date.issued | 2013-01-31 | en_US |
dc.identifier.govdoc | G06F012/02 | zh_TW |
dc.identifier.uri | http://hdl.handle.net/11536/105082 | - |
dc.description.abstract | Different processor elements in multi-task/multi-core system on chip may have different memory requirements at runtime. The method for adaptively allocating cache memory re-allocates the cache resource by updating the bank assignment table. According to the associativity-based partitioning scheme, centralized memory is separated into several groups of SRAM banks which are numbered differently. These groups are assigned to different processor elements to be L2 caches. The bank assignment information is recoded in bank assignment table, and is updated by system profiling engine. By changing the information in bank assignment table, the cache resource re-allocation for processor elements is achieved. | zh_TW |
dc.language.iso | zh_TW | en_US |
dc.title | SYSTEM AND METHOD FOR ALLOCATING CACHE MEMORY | zh_TW |
dc.type | Patents | en_US |
dc.citation.patentcountry | USA | zh_TW |
dc.citation.patentnumber | 20130031327 | zh_TW |
顯示於類別: | 專利資料 |