動態配罝即時編譯程式碼至草稿記憶體以利高效率爪哇執行

Abstract

現今不少嵌入式處理器除了配有快取記憶體(cache)外，也包含了草稿記憶體(scratch-pad memory)。對於這些處理器，有必要研究和開發一個機制來有效地利用草稿記憶體。目前沒有一個成功的草稿記憶體配置機制，能夠確實地在整個程式執行過程中，根據程式行為的變化來調整草稿記憶體的配置。此外，由於快取記憶體和主記憶體(main memory)之間的速度差異愈來愈大，指令快取誤失(instruction cache miss)所造成的停滯週期(stall cycles)已經成為程式執行時間裡相當大的一部分。對於爪哇(Java)程式，我們觀察到超過一半的停滯週期是即時編譯程式碼(JIT-compiled code)所引起的。為了減少指令快取誤失，我們提出了一個新的動態草稿記憶體配置機制來配置即時編譯程式碼至草稿記憶體，在此機制中草稿記憶體的配置可以隨著程式行為的變化而有所調整。

在我們的設計中，每個方法(method)被即時編譯器(JIT compiler)編譯時，都會先被配置到草稿記憶體。一旦草稿記憶體缺少空間，某些在草稿記憶體內的方法(method)會被重新配置至主記憶體。在程式執行過程中，即時編譯程式碼所造成的指令快取誤失的資訊會被蒐集，根據所蒐集的資訊，某些在主記憶體內的方法(method)會被重新配置至草稿記憶體。

實驗結果證實，對於配有快取記憶體和草稿記憶體的處理器，我們的設計能夠有效地利用草稿記憶體來減少指令快取誤失，進而改善程式執行效能；此設計的效能甚至比只配有快取記憶體且成本更高或相等的處理器還要好。

Nowadays, quite a few embedded processors have not only caches but also a scratch-pad memory (SPM). For these processors, it is essential to explore and develop a scheme to make good use of the SPM. There is no successful SPM allocation scheme proposed previously that can adjust SPM allocation exactly according to variations in the program behavior all the time throughout program execution. Furthermore, due to the widening speed gap between cache and main memory, stall cycles resulting from instruction cache misses have become a considerable part in the program execution time. For Java applications, we observed that over half of the instruction cache misses are caused by JIT-compiled code. Therefore, we proposed a novel dynamic SPM allocation scheme for JIT-compiled code to reduce instruction cache misses, in which the SPM allocation is adjustable according to variations in the program behavior.

In our design, every method is allocated to the SPM when it is compiled by the JIT compiler. Once the SPM lacks free space, certain methods in the SPM will be reallocated to the main memory. Throughout program execution, the information about instruction cache misses caused by JIT-compiled code is gathered, and certain JIT-compiled methods in the main memory would be reallocated to the SPM according to the gathered information.

The experimental results demonstrate that not only does our design make effective use of the SPM to reduce instruction cache misses and thus improve the program execution performance for the processors that have an instruction cache and an SPM, but it also has better performance than the processors only containing caches whose costs are higher than or the same as our design.