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dc.contributor.authorChang, Mu-Tienen_US
dc.contributor.authorHuang, Po-Tsangen_US
dc.contributor.authorHwang, Weien_US
dc.date.accessioned2014-12-16T06:15:33Z-
dc.date.available2014-12-16T06:15:33Z-
dc.date.issued2010-07-08en_US
dc.identifier.govdocG11C007/00zh_TW
dc.identifier.govdocG11C008/16zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/105393-
dc.description.abstractThe invention relates to a dual-threshold-voltage two-port sub-threshold SRAM cell apparatus. The above-mentioned apparatus comprises a first inverter, a second inverter, an access transistor and a read buffer. The first inverter and the second inverter include a plurality of first operating elements and a plurality of second operating elements for storing data. The access transistor is coupled to the first inverter and the second inverter, wherein the first operating elements and the second operating elements are high threshold voltage operating elements and the access transistor is low threshold voltage operating transistor. The read buffer is used for performing a read operation.zh_TW
dc.language.isozh_TWen_US
dc.titleDual-threshold-voltage two-port sub-threshold SRAM cell apparatuszh_TW
dc.typePatentsen_US
dc.citation.patentcountryUSAzh_TW
dc.citation.patentnumber20100172194zh_TW
Appears in Collections:Patents


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