標題: DIGITAL DELAY LINE AND APPLICATION THEREOF
作者: LEE, Chen-Yi
Yu, Jui-Yuan
Chen, Juinn-Ting
公開日期: 21-一月-2010
摘要: A digital delay line includes a plurality of hysteresis-based delay cells electrically connected in series. These hystersis delay units in the hysteresis-based delay cells may be similar or different. All of the hysteresis delay units respectively have an inverter mode and a hesteresis mode. The delay and resolution of the hysteresis delay unit may be derived from the time difference in the inverter mode and hysteresis mode. Such a digital delay line applied to a digital phase locked loop may reduce consumption of area and power.
官方說明文件#: H03L007/06
H03H011/26
URI: http://hdl.handle.net/11536/105450
專利國: USA
專利號碼: 20100013533
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