標題: | 應用於神經感測之面積與功耗最佳化11位元延遲線輔助之循序漸進式類比數位轉換器 Area-Power-Efficient 11-Bit SAR ADC with Delay-Line Enhanced Tuning for Neural Sensing Applications |
作者: | 黃騰頡 Huang, Teng-Chieh 莊景德 黃威 Chuang, Ching-Te Hwang, Wei 電子工程學系 電子研究所 |
關鍵字: | 類比數位轉換器;循序漸進式類比數位轉換器;延遲線;神經感測;自我時序;ADC;SAR;Delay-Line;Neural Sensing;Self-timed |
公開日期: | 2012 |
摘要: | 對於應用於高密度神經感測之生理訊號讀取系統來說,其所占據之面積與功耗是兩項嚴峻的挑戰。尤其對於由記錄放大器、類比數位轉換器和數位訊號處理電路構成的神經訊號紀錄處理系統,更是如此。有鑑於此,一顆具有面積與功耗最佳化之11位元混合式延遲線輔助之循序漸進式類比數位轉換器被應用在神經感測上並呈現於此論文中。更甚者,一具有4顆此混合式類比數位轉換器之16通道神經訊號感測系統被實現於2.5維度之異質整合上。為減少所使用之電容總量,提出的混合式類比數位轉換器是由3位元之延遲線類比數位轉換器做為粗調,並由8位元的循序漸進式類比數位轉換器實行微調。延遲線類比數位轉換器被設計用來偵測首三個最高有效位,經由一個電壓時間轉換器及一個調整過之量尺式時間數位轉換器所構成。為紓緩對於粗調的精準度要求,一種提升式搜尋演算法及再比一次方法於微調中採用。為更進一步節省功耗,分離式電容組以及非同步控制被使用於循序漸進式類比數位轉換器中。由聯華電子之180奈米互補式金屬氧化物半導體製程所製造,可以達到10.4位數之有效位元及每秒32000樣本數。除此之外,功耗為2.24微瓦,面積則是0.032平方毫米。而提出的混合式類比數位轉換器佐以延遲線輔助之品質系數為49.16飛焦耳/轉換 In a bio-signal acquisition system for high-density neural sensing applications, the occupied area and power consumption are two critical challenges for the neural recoding circuits consisting of recording amplifiers, analog-to-digital converters (ADCs) and digital processing circuits. In view of this, an area-power-efficient 11-bit hybrid ADC with delay-line enhanced tuning is presented for neural sensing applications in this thesis. Furthermore, a 16-channel neural recording system with 4 hybrid ADCs is implemented in a 2.5D heterogeneous integration. For reducing the total amount of capacitance, the proposed hybrid ADC is composed of a course tune and a fine tune by 3-bit delay-lined-based ADC and 8-bit successive approximation register (SAR) ADC, respectively. The delay-lined-based ADC is designed to detector the three MSBs by a voltage-to-time converter and a modified vernier time-to-digital converter. To relax the accuracy requirement of the coarse tune, the lifting-based searching algorithm and re-comparison procedure are proposed for the fine tune. In addition to further achieve energy saving, split capacitor array and self-timed control are utilized in the SAR ADC. Fabricated in UMC 180nm CMOS technology, an ENOB of 10.4-bit at 32KS/s can be achieved. Furthermore, the power consumption and area occupation are only 2.24μW and 0.032mm2, respectively. The FoM of the proposed hybrid ADC with delay-line enhanced tuning is 49.16fJ/conversion-step. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT070050212 http://hdl.handle.net/11536/71722 |
顯示於類別: | 畢業論文 |