應用於高密度神經元感測之11位元低電壓面積與功耗最佳化之類比數位轉換器

Abstract

在應用於高密度神經感測之生理訊號之訊號擷取系統中，紀錄放大器、類比數位轉換器以及數位訊號處理器所佔的面積以及功耗成為了嚴峻的挑戰。本論文提出了一個11位元功耗面積最佳化之類比數位轉換器。在本設計中，藉由將11位元類比數位轉換器拆成兩個部分設計─粗略調整類比數位轉換器以及精準調整類比數位轉換器進而達到降低電容大小的目的，相對於其他傳統設計省去約39%的面積。應用雙重供應電壓降低整體功耗但因此需要加上位準調整器當作低電壓訊號以及高電壓訊號的溝通平台。漏電流問題可以藉由電源門控功耗設計以及高臨界電壓的應用來解決。整體類比數位轉換器在取樣頻率32千取樣/每秒之下的功耗為418 奈瓦。有效位元是9.6位元而品質係數為16.2飛焦/轉換。整體類比數位轉換器之有效面積為0.0076平方毫米。

In a bio-signal acquisition system for high-density neural sensing applications, the occupied area and power consumption are two critical challenges for the neural recording circuits consisting of recording amplifiers, analog-to-digital converters (ADCs) and digital processing circuits. A 11-bit low voltage area-power-efficient SAR ADC is proposed. In our design, 11-bit ADC is separate into two parts, coarse tune ADC and fine tune ADC, in order to shrink capacitor size and achieve 39% smaller area than a conventional ADC. Appling dual voltage supply decreases power but needs level shifters as a communication platform between low and high voltage signal. Leakage problem is solved by power gating design and high threshold voltage implement. The ADC consumes 418 nW at sampling frequency 32 kS/s. The ENOB is 9.6-bit and the FoM is 16.2fJ/step. The active area of entire ADC is 0.0076 mm^2.