標題: | Area-Power-Efficient 11-Bit SAR ADC with Delay-Line Enhanced Tuning for Neural Sensing Applications |
作者: | Huang, Teng-Chieh Huang, Po-Tsang Wu, Shang-Lin Chen, Kuan-Neng Chiou, Jin-Chern Chen, Kuo-Hua Chiu, Chi-Tsung Tong, Ho-Ming Chuang, Ching-Te Hwang, Wei 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 2013 |
摘要: | In this paper, an area-power-efficient 11-bit hybrid analog-to-digital converter (ADC) with delay-line enhanced tuning for neural sensing applications is presented. To reduce the total amount of capacitance, this hybrid ADC is composed of a coarse tune and a fine tune by 3-bit delay-lined-based ADC and 8-bit successive approximation register (SAR) ADC, respectively. The delay-lined-based ADC is designed to detect the three most significant bits by a modified vernier structure. To relax the accuracy requirement of the coarse tune, the lifting-based searching algorithm and re-comparison procedure are proposed for the fine tune. To further achieve energy saving, split capacitor array and self-timed control are utilized in the SAR ADC. Fabricated in TSMC 0.18 mu m CMOS technology, an ENOB of 10.4-bit at 8KS/s can be achieved with only 0.6 mu W power consumption and 0.032-mm(2) area. The FoM of this ADC is 49.4fJ/conversion-step. |
URI: | http://hdl.handle.net/11536/24166 |
ISBN: | 978-1-4799-1471-5 |
ISSN: | 2163-4025 |
期刊: | 2013 IEEE BIOMEDICAL CIRCUITS AND SYSTEMS CONFERENCE (BIOCAS) |
起始頁: | 238 |
結束頁: | 241 |
顯示於類別: | 會議論文 |