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dc.contributor.authorLee, Tseng-Chinen_US
dc.contributor.authorTsui, Bing-Yueen_US
dc.contributor.authorTzeng, Pei-Jeren_US
dc.contributor.authorWang, Ching-Chiunen_US
dc.contributor.authorTsai, Ming-Jinnen_US
dc.date.accessioned2014-12-08T15:13:40Z-
dc.date.available2014-12-08T15:13:40Z-
dc.date.issued2010-05-01en_US
dc.identifier.issn0026-2714en_US
dc.identifier.urihttp://dx.doi.org/10.1016/j.microrel.2010.01.008en_US
dc.identifier.urihttp://hdl.handle.net/11536/10566-
dc.description.abstractCarbon nanotube field effect transistors (CNTFETs) have been considered as one of the potential candidates for nanoelectronics beyond Si CMOS. However, it is not easy to have high performance CNTFETs with high yield currently. In this work, we proposed a local bottom-gate (LBG) CNTFETs combined with a novel device concept and optimized process technologies. High performance of CNTFET with low subthreshold swing of 139 mV/dec, high transconductance of 1.27 mu S, and high I(on)/I(off) ratio of 10(6) can be easily obtained with Ti source/drain contact after a post annealing process. Record high yield of 74% has been demonstrated. On the basis of the proposed process, lots of high performance CNTFETs can be obtained easily for advanced study on the electrical characteristics of CNTFETs in the future. (C) 2010 Elsevier Ltd. All rights reserved.en_US
dc.language.isoen_USen_US
dc.titleA process for high yield and high performance carbon nanotube field effect transistorsen_US
dc.typeArticle; Proceedings Paperen_US
dc.identifier.doi10.1016/j.microrel.2010.01.008en_US
dc.identifier.journalMICROELECTRONICS RELIABILITYen_US
dc.citation.volume50en_US
dc.citation.issue5en_US
dc.citation.spage666en_US
dc.citation.epage669en_US
dc.contributor.department电子工程学系及电子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000278728700021-
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