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dc.contributor.authorChang, Edward Yien_US
dc.contributor.authorLee, Cheng-Shihen_US
dc.date.accessioned2014-12-16T06:16:17Z-
dc.date.available2014-12-16T06:16:17Z-
dc.date.issued2005-04-21en_US
dc.identifier.govdocH01L021/302zh_TW
dc.identifier.govdocH01L021/461zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/105748-
dc.description.abstractA bi-level structure based on copper metallization technique has been applied to backside of gallium arsenide (GaAs) devices. The foundation where the structure stands on is device substrate backside, on which a layer of diffusion barrier is deposited first, and to the top of it, a layer of copper metallization is plated to enhance device performance. The barrier layer can be selected from tungsten (W), tungsten nitride (WN), or titanium tungsten nitride (TiWN) by sputtering or evaporating, which effectively prevents copper from diffusing into GaAs substrate. The layer of copper metallization, formed by employing anyone of sputtering, evaporating, or electroplating, proves to offer attractive thermal and electrical conductivity and mechanical strength and the like. Moreover, these characteristic improvements coupled with a fascinating part, low cost, would benefit and motivate global GaAs fabs.zh_TW
dc.language.isozh_TWen_US
dc.titleMethod of fabricating copper metallization on backside of gallium arsenide deviceszh_TW
dc.typePatentsen_US
dc.citation.patentcountryUSAzh_TW
dc.citation.patentnumber20050085084zh_TW
Appears in Collections:Patents


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