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dc.contributor.authorChang, Hsie-Chiaen_US
dc.contributor.authorLee, Chen-Yien_US
dc.date.accessioned2014-12-16T06:16:21Z-
dc.date.available2014-12-16T06:16:21Z-
dc.date.issued2003-07-03en_US
dc.identifier.govdocH03M013/00zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/105791-
dc.description.abstractThe presently invention discloses a method for computing error locator polynomial and error evaluator polynomial in the key equation solving step of the error correction code decoding process whereby the polynomials are generated through at most t intermediate iterations that can be implemented with minimal amount of hardware circuitry. However, depending on the selected (N,K) code, the number of cycles required for the calculation of the polynomials would be within the time required for the calculation of upstream data. Additionally, the present invention for computing the error locator polynomial and the error value polynomial employs an efficient scheduling of a small number of registers and finite-field multipliers (FFMs) without the need of finite-field inverters (FFIs) is illustrated. Using these new methods, a new area-efficient architecture that uses only 4t+2ρ+4 registers and three FFMs and no FFIs is presented to implement the inversionless Euclidean algorithm.zh_TW
dc.language.isozh_TWen_US
dc.titleMethod and apparatus for solving key equation polynomials in decoding error correction codeszh_TW
dc.typePatentsen_US
dc.citation.patentcountryUSAzh_TW
dc.citation.patentnumber20030126543zh_TW
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